Cristina Marconcini

According to our database1, Cristina Marconcini authored at least 15 papers between 2003 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
On the integration of model-driven design and dynamic assertion-based verification for embedded software.
J. Syst. Softw., 2013

2011
Model-driven design and validation of embedded software.
Proceedings of the 6th International Workshop on Automation of Software Test, 2011

2008
An optimized CLP-based technique for generating propagation sequences.
Proceedings of the 2008 East-West Design & Test Symposium, 2008

2007
Improving high-level and gate-level testing with FATE: A functional automatic test pattern generator traversing unstabilised extended FSM.
IET Comput. Digit. Tech., 2007

A CLP-Based Functional ATPG for Extended FSMs.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

2006
Improving Gate-Level ATPG by Traversing Concurrent EFSMs.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

EFSM Manipulation to Increase High-Level ATPG Effectiveness.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

FATE: a Functional ATPG to Traverse Unstabilized EFSMs.
Proceedings of the 11th European Test Symposium, 2006

2005
Logic-level mapping of high-level faults.
Integr., 2005

A Pseudo-Deterministic Functional ATPG based on EFSM Traversing.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

An EFSM-based approach for functional ATPG.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004
A Verification Methodology for Reconfigurable Systems.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Functional verification based on the EFSM model.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage?
Proceedings of the 9th European Test Symposium, 2004

2003
Redundant functional faults reduction by saboteurs synthesis [logic verification].
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003


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