Andreas Sembrant

Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2017

A graphics tracing framework for exploring CPU+GPU memory systems.

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[DOI]

Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

Analyzing graphics workloads on tile-based GPUs.

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[DOI]

Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

A Split Cache Hierarchy for Enabling Data-Oriented Optimizations.

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[DOI]

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

POSTER: Putting the G back into GPU/CPU Systems Research.

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[DOI]

Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016

Hiding and Reducing Memory Latency : Energy-Efficient Pipeline and Memory System Techniques.

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[DOI]

PhD thesis, 2016

Data placement across the cache hierarchy: Minimizing data movement with reuse-aware placement.

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[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015

Long term parking (LTP): criticality-aware resource allocation in OOO processors.

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[DOI]

Proceedings of the 48th International Symposium on Microarchitecture, 2015

Cost-effective speculative scheduling in high performance processors.

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[DOI]

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

2014

Navigating the cache hierarchy with a single lookup.

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[DOI]

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

2013

TLC: a tag-less cache for reducing dynamic first level cache energy.

[BibT_eX]

[DOI]

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Modeling performance variation due to cache sharing.

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[DOI]

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012

Low Overhead Instruction-Cache Modeling Using Instruction Reuse Profiles.

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[DOI]

Muneeb Khan

Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

Power-Sleuth: A Tool for Investigating Your Program's Power Behavior.

[BibT_eX]

[DOI]

Vasileios Spiliopoulos

Stefanos Kaxiras

Proceedings of the 20th IEEE International Symposium on Modeling, 2012

Phase behavior in serial and parallel applications.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Workload Characterization, 2012

Phase guided profiling for fast cache modeling.

[BibT_eX]

[DOI]

Proceedings of the 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2012

2011

Efficient software-based online phase classification.

[BibT_eX]

[DOI]

David Eklov