Pierre Michaud

According to our database, Pierre Michaud authored at least 31 papers between 1996 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

HAIR: Halving the Area of the Integer Register File with Odd/Even Banking.

Pierre Michaud, Anis Peysieux

ACM Trans. Archit. Code Optim., 2022

2020

Exploiting Thermal Transients With Deterministic Turbo Clock Frequency.

Pierre Michaud

IEEE Comput. Archit. Lett., 2020

2018

An Alternative TAGE-like Conditional Branch Predictor.

Pierre Michaud

ACM Trans. Archit. Code Optim., 2018

2016

Some Mathematical Facts About Optimal Cache Replacement.

Pierre Michaud

ACM Trans. Archit. Code Optim., 2016

A simple proof of optimality for the MIN cache replacement policy.

Mun-Kyu Lee, Pierre Michaud, Jeong Seop Sim, DaeHun Nyang

Inf. Process. Lett., 2016

Best-offset hardware prefetching.

Pierre Michaud

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015

Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters.

Pierre Michaud, Andrea Mondelli, André Seznec

ACM Trans. Archit. Code Optim., 2015

BADCO: Behavioral Application-Dependent Superscalar Core Models.

Ricardo A. Velásquez, Pierre Michaud, André Seznec

Int. J. Parallel Program., 2015

Long term parking (LTP): criticality-aware resource allocation in OOO processors.

Andreas Sembrant, Trevor E. Carlson, Erik Hagersten, David Black-Schaffer, Arthur Perais, André Seznec, Pierre Michaud

Proceedings of the 48th International Symposium on Microarchitecture, 2015

Revisiting symbiotic job scheduling.

Stijn Eyerman, Pierre Michaud, Wouter Rogiest

Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

Cost-effective speculative scheduling in high performance processors.

Arthur Perais, André Seznec, Pierre Michaud, Andreas Sembrant, Erik Hagersten

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

2014

Multiprogram Throughput Metrics: A Systematic Approach.

Stijn Eyerman, Pierre Michaud, Wouter Rogiest

ACM Trans. Archit. Code Optim., 2014

2013

Demystifying multicore throughput metrics.

Pierre Michaud

IEEE Comput. Archit. Lett., 2013

Selecting benchmark combinations for the evaluation of multicore throughput.

Ricardo A. Velásquez, Pierre Michaud, André Seznec

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

2012

BADCO: Behavioral Application-Dependent Superscalar Core model.

Ricardo A. Velásquez, Pierre Michaud, André Seznec

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

2011

Replacement policies for shared caches on symmetric multicores: a programmer-centric point of view.

Pierre Michaud

Proceedings of the High Performance Embedded Architectures and Compilers, 2011

2010

Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses.

Pierre Michaud, Yiannakis Sazeides, André Seznec

Proceedings of the 7th Conference on Computing Frontiers, 2010

2009

Online compression of cache-filtered address traces.

Pierre Michaud

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009

2007

A study of thread migration in temperature-constrained multicores.

Pierre Michaud, André Seznec, Damien Fetis, Yiannakis Sazeides, Theofanis Constantinou

ACM Trans. Archit. Code Optim., 2007

2006

A case for (partially) TAgged GEometric history length branch prediction.

André Seznec, Pierre Michaud

J. Instr. Level Parallelism, 2006

2005

Performance implications of single thread migration on a chip multi-core.

Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Damien Fetis, André Seznec

SIGARCH Comput. Archit. News, 2005

A PPM-like, Tag-based Predictor.

Pierre Michaud

J. Instr. Level Parallelism, 2005

2004

Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration.

Pierre Michaud

Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

2003

A statistical model of skewed-associativity.

Pierre Michaud

Proceedings of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software, 2003

2002

A Learning Grid for the multichallenge school ECP.

Pierre Michaud, Christian Saguez

Proceedings of the 1st LEGE-WG International Workshop on Educational Models for GRID Based Services, 2002

2001

An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors.

Pierre Michaud, André Seznec, Stéphan Jourdan

Int. J. Parallel Program., 2001

Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors.

Pierre Michaud, André Seznec

Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

1999

Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors.

Pierre Michaud, André Seznec, Stéphan Jourdan

Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999

1997

Clustering techniques.

Pierre Michaud

Future Gener. Comput. Syst., 1997

Trading Conflict and Capacity Aliasing in Conditional Branch Predictors.

Pierre Michaud, André Seznec, Richard Uhlig

Proceedings of the 24th International Symposium on Computer Architecture, 1997

1996

Multiple-Block Ahead Branch Predictors.

André Seznec, Stéphan Jourdan, Pascal Sainrat, Pierre Michaud

Proceedings of the ASPLOS-VII Proceedings, 1996