Andres Asprilla

According to our database, Andres Asprilla authored at least 4 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Sequential Dual-Loop Digital and Analog PLL Synthesizer for Fast-Locking IoT Applications in 18nm FD-SOI CMOS.

Virgile Colrat, David Gaidioz, Andres Asprilla, Frédéric Paillardet, Andreia Cathelin, Yann Deval

Proceedings of the 17th IEEE Latin America Symposium on Circuits and System, 2026

2023

0.45-mW 2.35-3.0 GHz Multiplying DLL with Calibration Loop in 28nm CMOS FD-SOI.

Andres Asprilla, Andreia Cathelin, Yann Deval

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

Highly Linear Large Signal Compact Voltage-to-Current Converter in 28 nm FD-SOI Technology.

Andres Asprilla, Andreia Cathelin, Yann Deval

Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

2021

28nm FDSOI Ultra Low Power 1.5-2.0 GHz Factorial-DLL Frequency Synthesizer.

Andres Asprilla, David Cordova, Yann Deval, Hervé Lapuyade, François Rivet

IEEE Trans. Circuits Syst. II Express Briefs, 2021