Hervé Lapuyade
According to our database1,
Hervé Lapuyade
authored at least 34 papers
between 2000 and 2023.
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Bibliography
2023
A Proof-of-Concept of a Multiple-Cell Upsets Detection Method for SRAMs in Space Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
A Block-Based LMS Using the Walsh Transform for Digital Predistortion of Power Amplifiers.
IEEE Trans. Commun., October, 2023
A (0.75-1.13) mW and (2.4-5.2) ps RMS Jitter Integer-N-Based Dual-Loop PLL for Indoor and Outdoor Positioning in 28-nm FD-SOI CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
A Walsh-Based Arbitrary Waveform Generator for 5G Applications in 28nm FD-SOI CMOS Technology.
IEEE Access, 2023
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
2022
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
A 40 GHz Varactor-less Class-C VCO with 17.1% Tuning Range and Long-Term Reliability in 28nm FD-SOI for Satellite Communications.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
Optimized body-biasing calibration methodology for high-speed comparators in 22nm FDX.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
2020
Proceedings of the VLSI-SoC: Design Trends, 2020
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
2019
A Hierarchical Track and Hold Circuit for High Speed ADC-Based Receivers in 22nm FDSOI.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Design of CMOS integrated circuits for radiation hardening and its application to space electronics.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
2010
Fault Coverage on RF VCOs and BIST for Wafer Sort Using Peak-to-Peak Voltage Detectors.
J. Electron. Test., 2010
2009
Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Proceedings of the 2009 IEEE International Test Conference, 2009
2008
IEEE J. Solid State Circuits, 2008
2007
J. Electron. Test., 2007
Analog Design Considerations For Independently Driven Double Gate MOSfets And Their Application in a Low-Voltage OTA.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
A Low-Power and Low Silicon Area Testable CMOS LNA Dedicated to 802.15.4 Sensor Network Applications.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 11th European Test Symposium, 2006
2005
J. Low Power Electron., 2005
2003
Low-cost backside laser test method to pre-characterize the COTS IC's sensitivity to Single Event Effects.
Microelectron. Reliab., 2003
Proceedings of the ESSCIRC 2003, 2003
2001
Microelectron. Reliab., 2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
2000
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000