David Gaidioz

According to our database, David Gaidioz authored at least 3 papers between 2020 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Sequential Dual-Loop Digital and Analog PLL Synthesizer for Fast-Locking IoT Applications in 18nm FD-SOI CMOS.

Virgile Colrat, David Gaidioz, Andres Asprilla, Frédéric Paillardet, Andreia Cathelin, Yann Deval

Proceedings of the 17th IEEE Latin America Symposium on Circuits and System, 2026

2022

A Sub-100-μW 0.1-to-27-Mb/s Pulse-Based Digital Transmitter for the Human Intranet in 28-nm FD-SOI CMOS.

Guillaume Tochou, Robin Benarrouch, David Gaidioz, Andreia Cathelin, Antoine Frappé, Andreas Kaiser, Jan M. Rabaey

IEEE J. Solid State Circuits, 2022

2020

Ring VCO Phase Noise Optimization by Pseudo-Differential Architecture in 28nm FD-SOI CMOS.

David Gaidioz, Magali De Matos, Andreia Cathelin, Yann Deval

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020