Andreia Cathelin

According to our database1, Andreia Cathelin authored at least 85 papers between 2002 and 2021.

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Bibliography

2021
An Ultrafast Active Quenching Active Reset Circuit with 50% SPAD Afterpulsing Reduction in a 28 nm FD-SOI CMOS Technology Using Body Biasing Technique.
Sensors, 2021

16MB High Density Embedded PCM macrocell for automotive-grade microcontroller in 28nm FD-SOI, featuring extension to 24MB for Over-The-Air software update.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

An Active Quenching Circuit for a Native 3D SPAD Pixel in a 28 nm CMOS FDSOI Technology.
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021

A Low-Noise mm-Wave Injection-Locked Oscillator designed in 65nm Partially Depleted SOI CMOS Technology.
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021

A 250GHz Autodyne FMCW Radar in 55nm BiCMOS with Micrometer Range Resolution.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

F3: Silicon Technologies in the Fight Against Pandemics - From Point of Care to Computational Epidemiology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

F4: Electronics for a Quantum World.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

200-GS/s ADC Front-End Employing 25% Duty Cycle Quadrature Clock Generator.
Proceedings of the 47th ESSCIRC 2021, 2021

Artificial Intelligence: Why moving it to the Edge?
Proceedings of the 47th ESSCIRC 2021, 2021

An Energy Efficient Fully Integrated 20Gbps OOK Wireless Transmitter at 220GHz.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

Event-Driven Continuous-Time Feature Extraction for Ultra Low-Power Audio Keyword Spotting.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
Energy Efficient Heartbeat-Based MAC Protocol for WBAN Employing Body Coupled Communication.
IEEE Access, 2020

A Performance-Flexible Energy-Optimized Automotive-Grade Cortex-R4F SoC through Combined AVS/ABB/Bias-in-Memory-Array Closed-Loop Regulation in 28nm FD-SOI.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Ring VCO Phase Noise Optimization by Pseudo-Differential Architecture in 28nm FD-SOI CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Heartbeat-Based Synchronization Scheme for the Human Intranet: Modeling and Analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
A Spectrum-Sensing DPD Feedback Receiver With 30× Reduction in ADC Acquisition Bandwidth and Sample Rate.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 115-135-GHz 8PSK Receiver Using Multi-Phase RF-Correlation-Based Direct-Demodulation Method.
IEEE J. Solid State Circuits, 2019

Embedded PCM macro for automotive-grade microcontroller in 28nm FD-SOI.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Body-biasing considerations with SPAD FDSOI: advantages and drawbacks.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

A Single-Channel RF-to-Bits 36Gbps 8PSK RX with Direct Demodulation in RF Domain.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

Capacitive Body-Coupled Communication in the 400-500 MHz Frequency Band.
Proceedings of the Body Area Networks. Smart IoT and Big Data for Intelligent Health Management, 2019

2018
A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28-nm FD-SOI.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

All-Digital Transmitter Architecture Based on Two-Path Parallel 1-bit High Pass Filtering DACs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Comparative Study of On-Body Radio-Frequency Links in the 420 MHz-2.4 GHz Range.
Sensors, 2018

A bidirectional short range low power and high data rate W-Band transceiver for network on chip.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

90° Hybrid coupler design technique for wideband and multimode mm-wave operations featuring lateral ground planes virtual expansion in 28nm FD-SOI CMOS technology.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

A 301.7-to-331.8GHz source with entirely on-chip feedback loop for frequency stabilization in 0.μm BiCMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

FD-SOI integration solutions for analog, RF and Millimeter-wave applications.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

Integration of SPAD in 28nm FDSOI CMOS technology.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

2017
SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping.
IEEE J. Solid State Circuits, 2017

A 170-GHz Fully Integrated Single-Chip FMCW Imaging Radar with 3-D Imaging Capability.
IEEE J. Solid State Circuits, 2017

A High-Speed Efficient 220-GHz Spatial-Orthogonal ASK Transmitter in 130-nm SiGe BiCMOS.
IEEE J. Solid State Circuits, 2017

A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI.
IEEE J. Solid State Circuits, 2017

A 0.92-THz SiGe Power Radiator Based on a Nonlinear Theory for Harmonic Generation.
IEEE J. Solid State Circuits, 2017

27.5 A pixel-pitch-matched ultrasound receiver for 3D photoacoustic imaging with integrated delta-sigma beamformer in 28nm UTBB FDSOI.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

RF/analog and mixed-signal design techniques in FD-SOI technology.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
A 234-261-GHz 55-nm SiGe BiCMOS Signal Source with 5.4-7.2 dBm Output Power, 1.3% DC-to-RF Efficiency, and 1-GHz Divided-Down Output.
IEEE J. Solid State Circuits, 2016

A 2.4 GHz Interferer-Resilient Wake-Up Receiver Using A Dual-IF Multi-Stage N-Path Architecture.
IEEE J. Solid State Circuits, 2016

Introduction to the Special Issue on the 2015 Symposium on VLSI Circuits.
IEEE J. Solid State Circuits, 2016

A Fully Integrated 320 GHz Coherent Imaging Transceiver in 130 nm SiGe BiCMOS.
IEEE J. Solid State Circuits, 2016

55-nm SiGe BiCMOS Distributed Amplifier Topologies for Time-Interleaved 120-Gb/s Fiber-Optic Receivers and Transmitters.
IEEE J. Solid State Circuits, 2016

A concurrent transmitter in CMOS 28nm FDSOI technology based on Walsh sequences generator.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

25.5 A 320GHz subharmonic-mixing coherent imager in 0.13µm SiGe BiCMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Low power advanced digital technologies to enable Internet of Things.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

A digital delay line with coarse/fine tuning through gate/body biasing in 28nm FDSOI.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Sampling modulation: An energy efficient novel feature extraction for biosignal processing.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015
A SiGe Terahertz Heterodyne Imaging Transmitter With 3.3 mW Radiated Power and Fully-Integrated Phase-Locked Loop.
IEEE J. Solid State Circuits, 2015

A self-powered IPv6 bidirectional wireless sensor & actuator network for indoor conditions.
Proceedings of the Symposium on VLSI Circuits, 2015

Considerations for high-speed configurable-bandwidth time-interleaved digital delta-sigma modulators and synthesis in 28 nm UTBB FDSOI.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Design considerations for low-noise transconductance amplifiers in 28nm UTBB-FDSOI.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

13.5 A -97dBm-sensitivity interferer-resilient 2.4GHz wake-up receiver using dual-IF multi-N-Path architecture in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

5.5 A forward-body-bias tuned 450MHz Gm-C 3<sup>rd</sup>-order low-pass filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V supply.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

25.5 A 320GHz phase-locked transmitter with 3.3mW radiated power and 22.5dBm EIRP for heterodyne THz imaging systems.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization.
IEEE J. Solid State Circuits, 2014

2013
A digitally modulated mm-Wave cartesian beamforming transmitter with quadrature spatial combining.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A 7-Bit 18th Order 9.6 GS/s FIR Up-Sampling Filter for High Data Rate 60-GHz Wireless Transmitters.
IEEE J. Solid State Circuits, 2012

A 1 k-Pixel Video Camera for 0.7-1.1 Terahertz Imaging Applications in 65-nm CMOS.
IEEE J. Solid State Circuits, 2012

Gaining 10x in energy efficiency in the next decade in consumer products.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A 1kpixel CMOS camera chip for 25fps real-time terahertz imaging applications.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 65nm CMOS 1-to-10GHz tunable continuous-time low-pass filter for high-data-rate communications.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
A 65-nm CMOS Fully Integrated Transceiver Module for 60-GHz Wireless HD Applications.
IEEE J. Solid State Circuits, 2011

A 65nm CMOS fully integrated transceiver module for 60GHz wireless HD applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Towards personalized medicine and monitoring for healthy living.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 6.7-ENOB, 500-MS/s, 5.1-mW dynamic pipeline ADC in 65-nm SOI CMOS.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A 7-bit 18<sup>th</sup> order 9.6 GS/s FIR filter for high data rate 60-GHz wireless communications.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A 20-23GHz Coupled Oscillators Array in 65nm CMOS for HDR 60GHz beamforming applications.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

Design of 10 GHz sampling rate digital FIR filters with powers-of-two coefficients.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
A FIR baseband filter for high data rate 60-GHz wireless communications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
An All-Digital RF Signal Generator Using High-Speed ΔΣ Modulators.
IEEE J. Solid State Circuits, 2009

A combined 4-bit quadrature digital to analog converter/mixer for millimeter-wave applications.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

A 60GHz 65nm CMOS RMS power detector for antenna impedance mismatch detection.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
A 1.2 GHz semi-digital reconfigurable FIR bandpass filter with passive power combiner.
Proceedings of the ESSCIRC 2008, 2008

2007
A Switchable-Order G<sub>m</sub>-C Baseband Filter With Wide Digital Tuning for Configurable Radio Receivers.
IEEE J. Solid State Circuits, 2007

A 2GHz 0.25μm SiGe BiCMOS Oscillator with Flip-Chip Mounted BAW Resonator.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A Mixed Ladder-Lattice Bulk Acoustic Wave Duplexer for W-CDMA Handsets.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Digital tuning of an analog tunable bandpass BAW-filter at GHz frequency.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

80 GHz low noise amplifiers in 65nm CMOS SOI.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Design for millimeter-wave applications in silicon technologies.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Reconfigurable digital Delta-Sigma Modulator Synthesis for digital wireless transmitters.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
Design techniques for very high speed digital delta-sigma modulators aimed at all-digital RE transmitters.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
A 1 V 270 My-W 2 GHz CMOS Synchronized Ring Oscillator Based Prescaler.
J. Low Power Electron., 2005

Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A study on FBAR Filters reconfiguration.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

2002
Substrate Parasitic Extraction for RF Integrated Circuits.
Proceedings of the 2002 Design, 2002


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