Andrzej Pfitzner

According to our database1, Andrzej Pfitzner authored at least 10 papers between 2005 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2018
Optimization of the VeSFET Structure Dedicated to Basic Logic Cells in VeSTIC Technology.
Proceedings of the 25th International Conference "Mixed Design of Integrated Circuits and System", 2018

Feasibility Studies of EEPROM Memory Implementations in VeSTIC Technology.
Proceedings of the 25th International Conference "Mixed Design of Integrated Circuits and System", 2018

2016
Contribution to scaling of Vertical-Slit Field-Effect Transistor (VeSFET).
Proceedings of the 2016 MIXDES, 2016

2015
Compact DC model of a JVeSFET transistor with reduced number of empirical parameters.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

2014
Usefulness of VeSTIC devices for low-noise and radiation hard 3D integrated circuits.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

Improved simple DC model of Vertical-Slit Field-Effect Transistor (VeSFET).
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

2012
Vertical Slit Transistor based Integrated Circuits (VeSTICs).
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2009
Adder Circuits with Transistors using Independently Controlled Gates.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Is there always performance overhead for regular fabric?
Proceedings of the 26th International Conference on Computer Design, 2008

2005
Evaluation of parasitic capacitances for interconnection buses crossing in different layers.
Microelectron. Reliab., 2005


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