Dominik Kasprowicz

Orcid: 0000-0002-3480-6585

According to our database1, Dominik Kasprowicz authored at least 11 papers between 2001 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2019
Table-Based Model of a Dual-Gate Transistor for Statistical Circuit Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Semiconductor Device Parameter Extraction Based on I-V Measurements and Simulation.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

2017
Variability-aware table-based DC model of a dual-gate transistor.
Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

2015
Channel charge model of a dual-gate junctionless transistor.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

2014
Methods for automated detection of plagiarism in integrated-circuit layouts.
Microelectron. J., 2014

2013
Computer-aided detection of plagiarism in integrated-circuit layouts.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

VeSFET as an analog-circuit component.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2009
Adder Circuits with Transistors using Independently Controlled Gates.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Is there always performance overhead for regular fabric?
Proceedings of the 26th International Conference on Computer Design, 2008

2003
Improvement of integrated circuit testing reliability by using the defect based approach.
Microelectron. Reliab., 2003

2001
CMOS Standard Cells Characterization for Defect Based Testing.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001


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