Angelo Kuti Lusala

Orcid: 0000-0003-3162-3019

According to our database1, Angelo Kuti Lusala authored at least 13 papers between 2007 and 2023.

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Bibliography

2023
Design of an Asynchronous BCI Based on a Facial Expression Paradigm for the Remote Control of Robotic Systems.
Proceedings of the IEEE AFRICON 2023, Nairobi, Kenya, September 20-22, 2023, 2023

2017
Inner control loops approach to control the islanded photovoltaic microgrid.
Proceedings of the IEEE AFRICON 2017, Cape Town, South Africa, September 18-20, 2017, 2017

2015
A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs.
IEEE J. Solid State Circuits, 2015

2014
A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range.
Proceedings of the Symposium on VLSI Circuits, 2014

2012
A SDM-TDM-Based Circuit-Switched Router for On-Chip Networks.
ACM Trans. Reconfigurable Technol. Syst., 2012

Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks.
Int. J. Reconfigurable Comput., 2012

MPSoCDK: A framework for prototyping and validating MPSoC projects on FPGAs.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

A hybrid NoC combining SDM-TDM based circuit-switching with packet-switching for real-time applications.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

2011
A new mechanism to reduce congestion on TDM networks-on-chips.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Combining sdm-based circuit switching with packet switching in a NoC for real-time applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
A Hybrid Router Combining SDM-Based Circuit Swictching with Packet Switching for On-chip Networks.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Combining circuit and packet switching with bus architecture in a NoC for real-time applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2007
NoC Implementation in FPGA Using Torus Topology.
Proceedings of the FPL 2007, 2007


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