David Bol
Orcid: 0000-0002-2678-1613
According to our database1,
David Bol
authored at least 106 papers
between 2005 and 2024.
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Bibliography
2024
A Cradle-to-Gate Life Cycle Analysis of Bitcoin Mining Equipment Using Sphera LCA and ecoinvent Databases.
CoRR, 2024
2023
Technical and Ecological Limits of 2.45-GHz Wireless Power Transfer for Battery-Less Sensors.
IEEE Internet Things J., September, 2023
Bottom-Up and Top-Down Approaches for the Design of Neuromorphic Processing Systems: Tradeoffs and Synergies Between Natural and Artificial Intelligence.
Proc. IEEE, June, 2023
Evaluation and projection of 4G and 5G RAN energy footprints: the case of Belgium for 2020-2025.
Ann. des Télécommunications, June, 2023
A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023
Analysis and Design of RF Energy-Harvesting Systems With Impedance-Aware Rectifier Sizing.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
UFBBR: A Unified Frequency and Back-Bias Regulation Unit for Ultralow-Power Microcontrollers in 28-nm FDSOI.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
IEEE Open J. Circuits Syst., 2023
IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm<sup>2</sup> CIM-SRAM With Multi-Bit Analog Batch-Normalization.
IEEE J. Solid State Circuits, 2023
A 1.1-/0.9-nA Temperature-Independent 213-/565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI.
IEEE J. Solid State Circuits, 2023
A 1.1- / 0.9-nA Temperature-Independent 213- / 565-ppm/$^\circ$C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI.
CoRR, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Comprehensive Analytical Comparison of Ring Oscillators in FDSOI Technology: Current Starving Versus Back-Bias Control.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-μm With 0.1-nA PTAT and 1.1-μA CWT 38-ppm/°C Designs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Accurate and Insightful Closed-Form Prediction of Subthreshold SRAM Hold Failure Rate.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Biomed. Circuits Syst., 2022
IEEE Internet Things J., 2022
From Silicon Shield to Carbon Lock-in ? The Environmental Footprint of Electronic Components Manufacturing in Taiwan (2015-2020).
CoRR, 2022
Modeling the Carbon Footprint of Battery-Powered IoT Sensor Nodes for Environmental-Monitoring Applications.
Proceedings of the 12th International Conference on the Internet of Things, 2022
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022
A 0.9-nA Temperature-Independent 565-ppm/°C Self-Biased Current Reference in 22-nm FDSOI.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Mixed-Signal Compensation of Tripolar Cuff Electrode Imbalance in a Low-Noise ENG Analog Front-End.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
A Configurable ULP Instrumentation Amplifier With Pareto-Optimal Power-Noise Trade-Off Achieving 1.93 NEF in 65nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Impact of Analog Non-Idealities on the Design Space of 6T-SRAM Current-Domain Dot-Product Operators for In-Memory Computing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Open J. Commun. Soc., 2021
A Self-Gating RF Energy Harvester for Wireless Power Transfer With High-PAPR Incident Waveform.
IEEE J. Solid State Circuits, 2021
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode.
IEEE J. Solid State Circuits, 2021
Bottom-Up and Top-Down Neural Processing Systems Design: Neuromorphic Intelligence as the Convergence of Natural and Artificial Intelligence.
CoRR, 2021
Assessing the embodied carbon footprint of IoT edge devices with a bottom-up life-cycle approach.
CoRR, 2021
SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
A 0.2-to-3.6TOPS/W Programmable Convolutional Imager SoC with In-Sensor Current-Domain Ternary-Weighted MAC Operations for Feature Extraction and Region-of-Interest Detection.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021
2020
IEEE Trans. Circuits Syst., 2020
A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A 0.086-mm<sup>2</sup> 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS.
IEEE Trans. Biomed. Circuits Syst., 2019
MorphIC: A 65-nm 738k-Synapse/mm<sup>2</sup> Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning.
IEEE Trans. Biomed. Circuits Syst., 2019
Analysis, Modeling, and Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT Smart Sensors.
IEEE J. Solid State Circuits, 2019
A battery-less BLE smart sensor for room occupancy tracking supplied by 2.45-GHz wireless power transfer.
Integr., 2019
Learning without feedback: Direct random target projection as a feedback-alignment algorithm with layerwise feedforward training.
CoRR, 2019
A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A 65-nm 738k-Synapse/mm<sup>2</sup> Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
A Robust 10-Gb/s Duobinary Transceiver in 0.13-μm SOI CMOS for Short-Haul Optical Networks.
IEEE Trans. Ind. Electron., 2018
A 0.4-V 0.66-fJ/Cycle Retentive True-Single-Phase-Clock 18T Flip-Flop in 28-nm Fully-Depleted SOI CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Analysis and Specification of an IR-UWB Transceiver for High-Speed Chip-to-Chip Communication in a Server Chassis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 0.086-mm<sup>2</sup> 9.8-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS.
CoRR, 2018
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security, 2018
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping.
IEEE J. Solid State Circuits, 2017
Architecture exploration of a fixed point computation unit using precise timing spiking neurons.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
A 0.4V 0.08fJ/cycle retentive True-Single-Phase-Clock 18T Flip-Flop in 28nm FDSOI CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A fully-synthesized 20-gate digital spike-based synapse with embedded online learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
2016
Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI.
Microelectron. J., 2016
SleepTalker: A 28nm FDSOI ULV 802.15.4a IR-UWB transmitter SoC achieving 14pJ/bit at 27Mb/s with adaptive-FBB-based channel selection and programmable pulse shape.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Comparative analysis of redundancy schemes for soft-error detection in low-cost space applications.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016
Sizing and layout integrated optimizer for 28nm analog circuits using digital PnR tools.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016
2015
A Capacitance-to-Frequency Converter With On-Chip Passivated Microelectrodes for Bacteria Detection in Saline Buffers Up to 575 MHz.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs.
IEEE J. Solid State Circuits, 2015
A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 0.48mm<sup>2</sup> 5μW-10mW indoor/outdoor PV energy-harvesting management unit in a 65nm SoC based on a single bidirectional multi-gain/multi-mode switched-cap converter with supercap storage.
Proceedings of the ESSCIRC Conference 2015, 2015
2014
Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2014
A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks.
IEEE Trans. Emerg. Top. Comput., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations.
J. Low Power Electron., 2014
A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range.
Proceedings of the Symposium on VLSI Circuits, 2014
Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
SleepWalker: A 25-MHz 0.4-V Sub-mm<sup>2</sup> 7-µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes.
IEEE J. Solid State Circuits, 2013
Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
An efficient metric of setup time for pulsed flip-flops based on output transition time.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
2012
A Fast ULV Logic Synthesis Flow in Many-V<sub>t</sub> CMOS Processes for Minimum Energy Under Timing Constraints.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Towards Green Cryptography: A Comparison of Lightweight Ciphers from the Energy Viewpoint.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2012, 2012
2011
Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags.
J. Cryptogr. Eng., 2011
Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-threshold Devices through an Example of a 65nm AES Implementation.
Proceedings of the RFID. Security and Privacy - 7th International Workshop, 2011
2010
Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic - Mitigation at Technology and Circuit Levels.
ACM Trans. Design Autom. Electr. Syst., 2010
Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Glitch-induced within-die variations of dynamic energy in voltage-scaled nano-CMOS circuits.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 26th International Conference on Computer Design, 2008
2007
Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder.
J. Multiple Valued Log. Soft Comput., 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications.
J. Low Power Electron., 2006
Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
2005
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications.
Proceedings of the Integrated Circuit and System Design, 2005