David Bol

According to our database1, David Bol authored at least 66 papers between 2005 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A 0.086-mm2 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS.
IEEE Trans. Biomed. Circuits and Systems, 2019

MorphIC: A 65-nm 738k-Synapse/mm2 Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning.
IEEE Trans. Biomed. Circuits and Systems, 2019

Analysis, Modeling, and Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT Smart Sensors.
J. Solid-State Circuits, 2019

A battery-less BLE smart sensor for room occupancy tracking supplied by 2.45-GHz wireless power transfer.
Integration, 2019

Learning without feedback: Direct random target projection as a feedback-alignment algorithm with layerwise feedforward training.
CoRR, 2019

A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 65-nm 738k-Synapse/mm2 Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits.
IEEE Trans. VLSI Syst., 2018

A Robust 10-Gb/s Duobinary Transceiver in 0.13-μm SOI CMOS for Short-Haul Optical Networks.
IEEE Trans. Industrial Electronics, 2018

A 0.4-V 0.66-fJ/Cycle Retentive True-Single-Phase-Clock 18T Flip-Flop in 28-nm Fully-Depleted SOI CMOS.
IEEE Trans. on Circuits and Systems, 2018

Analysis and Specification of an IR-UWB Transceiver for High-Speed Chip-to-Chip Communication in a Server Chassis.
IEEE Trans. on Circuits and Systems, 2018

A 0.086-mm2 9.8-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS.
CoRR, 2018

A Battery-Less BLE IoT Motion Detector Supplied by 2.45-GHz Wireless Power Transfer.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Low-power half-rate dual-loop clock-recovery system in 28-nm FDSOI.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Demonstrating an LPPN Processor.
Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security, 2018

Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT smart sensors.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping.
J. Solid-State Circuits, 2017

Architecture exploration of a fixed point computation unit using precise timing spiking neurons.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

A 0.4V 0.08fJ/cycle retentive True-Single-Phase-Clock 18T Flip-Flop in 28nm FDSOI CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A fully-synthesized 20-gate digital spike-based synapse with embedded online learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

A compact phenomenological digital neuron implementing the 20 Izhikevich behaviors.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI.
Microelectronics Journal, 2016

SleepTalker: A 28nm FDSOI ULV 802.15.4a IR-UWB transmitter SoC achieving 14pJ/bit at 27Mb/s with adaptive-FBB-based channel selection and programmable pulse shape.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Comparative analysis of redundancy schemes for soft-error detection in low-cost space applications.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Towards Securing Low-Power Digital Circuits with Ultra-Low-Voltage Vdd Randomizers.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016

Sizing and layout integrated optimizer for 28nm analog circuits using digital PnR tools.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

CAMEL: An Ultra-Low-Power VGA CMOS Imager based on a Time-Based DPS Array.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

2015
A Capacitance-to-Frequency Converter With On-Chip Passivated Microelectrodes for Bacteria Detection in Saline Buffers Up to 575 MHz.
IEEE Trans. on Circuits and Systems, 2015

A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs.
J. Solid-State Circuits, 2015

A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Analysis and optimization for dynamic read stability in 28nm SRAM bitcells.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 0.48mm2 5μW-10mW indoor/outdoor PV energy-harvesting management unit in a 65nm SoC based on a single bidirectional multi-gain/multi-mode switched-cap converter with supercap storage.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits.
IEEE Trans. VLSI Syst., 2014

A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks.
IEEE Trans. Emerging Topics Comput., 2014

A Sizing Methodology for On-Chip Switched-Capacitor DC/DC Converters.
IEEE Trans. on Circuits and Systems, 2014

A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations.
J. Low Power Electronics, 2014

A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range.
Proceedings of the Symposium on VLSI Circuits, 2014

Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
SleepWalker: A 25-MHz 0.4-V Sub-mm2 7-µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes.
J. Solid-State Circuits, 2013

Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

An efficient metric of setup time for pulsed flip-flops based on output transition time.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

2012
A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy Under Timing Constraints.
IEEE Trans. on Circuits and Systems, 2012

Pushing Adaptive Voltage Scaling Fully on Chip.
J. Low Power Electronics, 2012

A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Towards Green Cryptography: A Comparison of Lightweight Ciphers from the Energy Viewpoint.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2012, 2012

2011
Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags.
J. Cryptographic Engineering, 2011

Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-threshold Devices through an Example of a 65nm AES Implementation.
Proceedings of the RFID. Security and Privacy - 7th International Workshop, 2011

2010
Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic - Mitigation at Technology and Circuit Levels.
ACM Trans. Design Autom. Electr. Syst., 2010

Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Interests and Limitations of Technology Scaling for Subthreshold Logic.
IEEE Trans. VLSI Syst., 2009

Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2008
Impact of Technology Scaling on Digital Subthreshold Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Analysis and minimization of practical energy in 45nm subthreshold logic circuits.
Proceedings of the 26th International Conference on Computer Design, 2008

2007
Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder.
Multiple-Valued Logic and Soft Computing, 2007

Building Ultra-Low-Power Low-Frequency Digital Circuits with High-Speed Devices.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications.
J. Low Power Electronics, 2006

Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications.
Proceedings of the Integrated Circuit and System Design, 2005


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