Anup Holey

According to our database1, Anup Holey authored at least 7 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Trans-FW: Short Circuiting Page Table Walk in Multi-GPU Systems via Remote Forwarding.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2015
Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor.
ACM Trans. Archit. Code Optim., 2015

2014
Lightweight Software Transactions on GPUs.
Proceedings of the 43rd International Conference on Parallel Processing, 2014

2013
Accelerating Data Race Detection Utilizing On-Chip Data-Parallel Cores.
Proceedings of the Runtime Verification - 4th International Conference, 2013

HAccRG: Hardware-Accelerated Data Race Detection in GPUs.
Proceedings of the 42nd International Conference on Parallel Processing, 2013

Managing shared last-level cache in a heterogeneous multicore processor.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012


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