Antonia Zhai

According to our database1, Antonia Zhai authored at least 50 papers between 2000 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
GranularNF: Granular Decomposition of Stateful NFV at 100 Gbps Line Speed and Beyond.
SIGMETRICS Perform. Evaluation Rev., August, 2022

PREDATOR: A Cache Side-Channel Attack Detector Based on Precise Event Monitoring.
Proceedings of the 2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED), 2022

2020
In-Network Memory Access Ordering for Heterogeneous Multicore Systems.
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020

First Time Miss : Low Overhead Mitigation for Shared Memory Cache Side Channels.
Proceedings of the ICPP 2020: 49th International Conference on Parallel Processing, 2020

Efficient and scalable cross-ISA virtualization of hardware transactional memory.
Proceedings of the CGO '20: 18th ACM/IEEE International Symposium on Code Generation and Optimization, 2020

2019
New Attacks and Defenses for Randomized Caches.
CoRR, 2019

Unleashing the Power of Learning: An Enhanced Learning-Based Approach for Dynamic Binary Translation.
Proceedings of the 2019 USENIX Annual Technical Conference, 2019

2018
Enhancing Cross-ISA DBT Through Automatically Learned Translation Rules.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Enabling Cross-ISA Offloading for COTS Binaries.
Proceedings of the 15th Annual International Conference on Mobile Systems, 2017

2016
A General Persistent Code Caching Framework for Dynamic Binary Translation (DBT).
Proceedings of the 2016 USENIX Annual Technical Conference, 2016

2015
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures.
ACM Trans. Comput. Syst., 2015

Leveraging Transactional Execution for Memory Consistency Model Emulation.
ACM Trans. Archit. Code Optim., 2015

Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor.
ACM Trans. Archit. Code Optim., 2015

2014
Measuring Microarchitectural Details of Multi- and Many-Core Memory Systems through Microbenchmarking.
ACM Trans. Archit. Code Optim., 2014

Efficient Spatial Processing Element Control via Triggered Instructions.
IEEE Micro, 2014

Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for Heterogeneous Multicore Systems.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

Multi-stage coordinated prefetching for present-day processors.
Proceedings of the 2014 International Conference on Supercomputing, 2014

Lightweight Software Transactions on GPUs.
Proceedings of the 43rd International Conference on Parallel Processing, 2014

2013
The design and implementation of heterogeneous multicore systems for energy-efficient speculative thread execution.
ACM Trans. Archit. Code Optim., 2013

Accelerating Data Race Detection Utilizing On-Chip Data-Parallel Cores.
Proceedings of the Runtime Verification - 4th International Conference, 2013

Triggered instructions: a control paradigm for spatially-programmed architectures.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

HAccRG: Hardware-Accelerated Data Race Detection in GPUs.
Proceedings of the 42nd International Conference on Parallel Processing, 2013

Managing shared last-level cache in a heterogeneous multicore processor.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
Dynamically dispatching speculative threads to improve sequential execution.
ACM Trans. Archit. Code Optim., 2012

Code Transformations for Enhancing the Performance of speculatively Parallel Threads.
J. Circuits Syst. Comput., 2012

Effectiveness of Compiler-Directed Prefetching on Data Mining Benchmarks.
J. Circuits Syst. Comput., 2012

Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

2011
Efficient dynamic program monitoring on multi-core systems.
J. Syst. Archit., 2011

NoC frequency scaling with flexible-pipeline routers.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Enabling improved power management in multicore processors through clustered DVFS.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Improving the performance of program monitors with compiler support in multi-core environment.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Energy efficient speculative threads: dynamic thread allocation in Same-ISA heterogeneous multicore systems.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
Hardware Supported Flexible Monitoring: Early Results.
Proceedings of the Runtime Verification, 9th International Workshop, 2009

Exploring speculative parallelism in SPEC2006.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009

Dynamic performance tuning for speculative threads.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Exploiting TLS Parallelism at Multiple Loop-Nest Levels.
Proceedings of the 15th IEEE International Conference on Parallel and Distributed Systems, 2009

2008
Compiler and hardware support for reducing the synchronization of speculative threads.
ACM Trans. Archit. Code Optim., 2008

Compiler optimizations for parallelizing general-purpose applications under thread-level speculation.
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2008

Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective.
Proceedings of the 26th International Conference on Computer Design, 2008

2006
Exploiting Speculative Thread-Level Parallelism in Data Compression Applications.
Proceedings of the Languages and Compilers for Parallel Computing, 2006

Supporting Speculative Multithreading on Simultaneous Multithreaded Processors.
Proceedings of the High Performance Computing, 2006

A Study of the Performance Potential for Dynamic Instruction Hints Selection.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

Issues and Support for Dynamic Register Allocation.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005
The STAMPede approach to thread-level speculation.
ACM Trans. Comput. Syst., 2005

Loop Selection for Thread-Level Speculation.
Proceedings of the Languages and Compilers for Parallel Computing, 2005

A General Compiler Framework for Speculative Optimizations Using Data Speculative Code Motion.
Proceedings of the 3nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2005), 2005

2004
Compiler Optimization of Memory-Resident Value Communication Between Speculative Threads.
Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004

2002
Improving Value Communication for Thread-Level Speculation.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

Compiler optimization of scalar value communication between speculative threads.
Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), 2002

2000
A scalable approach to thread-level speculation.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000


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