Youtao Zhang

According to our database1, Youtao Zhang authored at least 143 papers between 2000 and 2019.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepage:

On csauthors.net:

Bibliography

2019
A Novel STT-RAM-Based Hybrid Cache for Intermittently Powered Processors in IoT Devices.
IEEE Micro, 2019

PageCmp: Bandwidth Efficient Page Deduplication through In-memory Page Comparison.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

RFAcc: a 3D ReRAM associative array based random forest accelerator.
Proceedings of the ACM International Conference on Supercomputing, 2019

ROC: DRAM-based Processing with Reduced Operation Cycles.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

H-ORAM: A Cacheable ORAM Interface for Efficient I/O Accesses.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Leveraging Approximate Data for Robust Flash Storage.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

LAcc: Exploiting Lookup Table-based Fast and Accurate Vector Multiplication in DRAM-based CNN Accelerator.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A Framework for Memory Oversubscription Management in Graphics Processing Units.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

Boosting chipkill capability under retention-error induced reliability emergency.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

ApproxFTL: On the Performance and Lifetime Improvement of 3-D NAND Flash-Based SSDs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A 1.2 GSps, 8 bit RF DAC for multi-Nyquist applications in GaAs technology.
IEICE Electronic Express, 2018

Time-aware cloud service recommendation using similarity-enhanced collaborative filtering and ARIMA model.
Decision Support Systems, 2018

Exploring diffusion strategies for mHealth promotion using evolutionary game model.
Applied Mathematics and Computation, 2018

Enabling Intra-Plane Parallel Block Erase in NAND Flash to Alleviate the Impact of Garbage Collection.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

D-ORAM: Path-ORAM Delegation for Low Execution Interference on Cloud Servers with Untrusted Memory.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

ShadowGC: Cooperative garbage collection with multi-level buffer for performance improvement in NAND flash-based SSDs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Wear leveling for crossbar resistive memory.
Proceedings of the 55th Annual Design Automation Conference, 2018

DrAcc: a DRAM based accelerator for accurate CNN inference.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
On the Restore Time Variations of Future DRAM Memory.
ACM Trans. Design Autom. Electr. Syst., 2017

Optimizing power efficiency for 3D stacked GPU-in-memory architecture.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

A 2 GSps, 8-Bit Folding and Interpolation ADC with Foreground Calibration in 90 nm CMOS Technology.
J. Sensors, 2017

Multi-objective optimization based ranking prediction for cloud service recommendation.
Decision Support Systems, 2017

Decongest: Accelerating Super-Dense PCM Under Write Disturbance by Hot Page Remapping.
Computer Architecture Letters, 2017

Mitigating shift-based covert-channel attacks in racetrack last level caches.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

Constructing fast and energy efficient 1TnR based ReRAM crossbar memory.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Quality of Service Support for Fine-Grained Sharing on GPUs.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Read Error Resilient MLC STT-MRAM Based Last Level Cache.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

AEP: An error-bearing neural network accelerator for energy efficiency and model protection.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Speeding up crossbar resistive memory by exploiting in-memory data patterns.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Towards warp-scheduler friendly STT-RAM/SRAM hybrid GPGPU register file design.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Cooperative Path-ORAM for Effective Memory Bandwidth Sharing in Server Settings.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

DrMP: Mixed Precision-Aware DRAM for High Performance Approximate and Precise Computing.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
Simultaneous Multikernel: Fine-Grained Sharing of GPUs.
Computer Architecture Letters, 2016

Live code update for IoT devices in energy harvesting environments.
Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016

AWARD: Approximation-aWAre Restore in Further Scaling DRAM.
Proceedings of the Second International Symposium on Memory Systems, 2016

Restore truncation for performance improvement in future DRAM systems.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Simultaneous Multikernel GPU: Multi-tasking throughput processors via fine-grained sharing.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

ReadDuo: Constructing Reliable MLC Phase Change Memory through Fast and Robust Readout.
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2016

Checkpoint aware hybrid cache architecture for NV processor in energy harvesting powered systems.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

2015
Simple Virtual Channel Allocation for High-Throughput and High-Frequency On-Chip Routers.
TOPC, 2015

Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM Technology.
ACM Trans. Design Autom. Electr. Syst., 2015

Wear Relief for High-Density Phase Change Memory Through Cell Morphing Considering Process Variation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Achieving Yield, Density and Performance Effective DRAM at Extreme Technology Sizes.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

Exploit common source-line to construct energy efficient domain wall memory based caches.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

TriState-SET: Proactive SET for improved performance of MLC phase change memories.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

DLB: Dynamic lane borrowing for improving bandwidth and performance in Hybrid Memory Cube.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

GA Based Placement Optimization for Hybrid Distributed Storage.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Exploiting DRAM restore time variations in deep sub-micron scaling.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Selective restore: an energy efficient read disturbance mitigation scheme for future STT-MRAM.
Proceedings of the 52nd Annual Design Automation Conference, 2015

SD-PCM: Constructing Reliable Super Dense Phase Change Memory under Write Disturbance.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014
Throughput Enhancement for Phase Change Memories.
IEEE Trans. Computers, 2014

Errata to "Process Variation-Aware Nonuniform Cache Management in a 3D Die-Stacked Multicore Processor".
IEEE Trans. Computers, 2014

Combining QoS prediction and customer satisfaction estimation to solve cloud service trustworthiness evaluation problems.
Knowl.-Based Syst., 2014

A low power and reliable charge pump design for Phase Change Memories.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

R-Dedup: Content Aware Redundancy Management for SSD-Based RAID Systems.
Proceedings of the 43rd International Conference on Parallel Processing, 2014

Dual-Page Mode: Exploring Parallelism in MLC Flash SSDs.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

Mitigating Write Disturbance in Super-Dense Phase Change Memories.
Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2014

SLC-enabled Wear Leveling for MLC PCM Considering Process Variation.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

CD-RAIS: Constrained dynamic striping in redundant array of independent SSDs.
Proceedings of the 2014 IEEE International Conference on Cluster Computing, 2014

2013
Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices.
ACM Trans. Design Autom. Electr. Syst., 2013

Process Variation-Aware Nonuniform Cache Management in a 3D Die-Stacked Multicore Processor.
IEEE Trans. Computers, 2013

Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory.
TACO, 2013

A speculative arbiter design to enable high-frequency many-VC router in NoCs.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Compiler directed write-mode selection for high performance low power volatile PCM.
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2013

WoM-SET: Low power proactive-SET-based PCM write using WoM code.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

The design of sustainable wireless sensor network node using solar energy and phase change memory.
Proceedings of the Design, Automation and Test in Europe, 2013

Low cost power failure protection for MLC NAND flash storage systems with PRAM/DRAM hybrid buffer.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

ER: elastic RESET for low power and long endurance MLC based phase change memory.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Improving write operations in MLC phase change memory.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Architecting a common-source-line array for bipolar non-volatile memory devices.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
A co-commitment based secure data collection scheme for tiered wireless sensor networks.
Journal of Systems Architecture - Embedded Systems Design, 2011

Analyzing the impact of useless write-backs on the endurance and energy consumption of PCM main memory.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

Enhancing phase change memory lifetime through fine-grained current regulation and voltage upscaling.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

A composite and scalable cache coherence protocol for large scale CMPs.
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory.
Proceedings of the 2011 IEEE/IFIP International Conference on Dependable Systems and Networks, 2011

Proactive recovery for BTI in high-k SRAM cells.
Proceedings of the Design, Automation and Test in Europe, 2011

Emerging non-volatile memories: opportunities and challenges.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache Replacement.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
The design and evaluation of interleaved authentication for filtering false reports in multipath routing WSNs.
Wireless Networks, 2010

Thermal-Aware Task Scheduling for 3D Multicore Processors.
IEEE Trans. Parallel Distrib. Syst., 2010

Performance-aware thermal management via task scheduling.
TACO, 2010

Phase-Change Technology and the Future of Main Memory.
IEEE Micro, 2010

A low-cost memory remapping scheme for address bus protection.
J. Parallel Distrib. Comput., 2010

An authentication scheme for locating compromised sensor nodes in WSNs.
J. Network and Computer Applications, 2010

An efficient code update scheme for DSP applications in mobile embedded systems.
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

Fine-grained QoS scheduling for PCM-based main memory systems.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Simple virtual channel allocation for high throughput and high frequency on-chip routers.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Proactive NBTI mitigation for busy functional units in out-of-order microprocessors.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Towards update-conscious compilation for energy-efficient code dissemination in WSNs.
TACO, 2009

Special issue of selected papers from EUC 2005.
J. Embedded Computing, 2009

Supporting flexible streaming media protection through privacy-aware secure processors.
Computers & Electrical Engineering, 2009

SDC: Secure Data Collection for Time Based Queries in Tiered Wireless Sensor Networks.
Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2009

Variation-tolerant non-uniform 3D cache management in die stacked multicore processor.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

A durable and energy efficient main memory using phase change memory technology.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Energy reduction for STT-RAM using early write termination.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A low-radix and low-diameter 3D interconnection network design.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

MCP: An Energy-Efficient Code Distribution Protocol for Multi-Application WSNs.
Proceedings of the Distributed Computing in Sensor Systems, 2009

Frequent value compression in packet-based NoC architectures.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Dynamic Thermal Management through Task Scheduling.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

Towards energy-efficient code dissemination in wireless sensor networks.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Thermal Management for 3D Processors via Task Scheduling.
Proceedings of the 2008 International Conference on Parallel Processing, 2008

Adaptive Buffer Management for Efficient Code Dissemination in Multi-Application Wireless Sensor Networks.
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

2007
The design and evaluation of path matching schemes on compressed control flow traces.
Journal of Systems and Software, 2007

UCC: update-conscious compilation for energy efficiency in wireless sensor networks.
Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, 2007

2006
Compressing heap data for improved memory performance.
Softw., Pract. Exper., 2006

Dynamic Authentication-Key Re-assignment for Reliable Report Delivery.
Proceedings of the IEEE 3rd International Conference on Mobile Adhoc and Sensor Systems, 2006

The interleaved authentication for filtering false reports in multipath routing based sensor networks.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Reduce Register Files Leakage Through Discharging Cells.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

InfoShield: a security architecture for protecting information usage in memory.
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

Locating Compromised Sensor Nodes Through Incremental Hashing Authentication.
Proceedings of the Distributed Computing in Sensor Systems, 2006

Efficient Group KeyManagement with Tamper-resistant ISA Extensions.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

A low-cost memory remapping scheme for address bus protection.
Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005
Cost and precision tradeoffs of dynamic data slicing algorithms.
ACM Trans. Program. Lang. Syst., 2005

Improving Memory Encryption Performance in Secure Processors.
IEEE Trans. Computers, 2005

Architectural support for protecting user privacy on trusted processors.
SIGARCH Computer Architecture News, 2005

A low energy cache design for multimedia applications exploiting set access locality.
Journal of Systems Architecture, 2005

Reducing I-cache energy of multimedia applications through low cost tag comparison elimination.
J. Embedded Computing, 2005

Supporting efficient query processing on compressed XML files.
Proceedings of the 2005 ACM Symposium on Applied Computing (SAC), 2005

Dynamic Co-allocation of Level One Caches.
Proceedings of the Embedded Software and Systems, Second International Conference, 2005

SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

Performance Comparison of Path Matching Algorithms over Compressed Control Flow Traces.
Proceedings of the 2005 Data Compression Conference (DCC 2005), 2005

2004
Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors.
IJHPCN, 2004

Speculative Subword Register Allocation in Embedded Processors.
Proceedings of the Languages and Compilers for High Performance Computing, 2004

Efficient Forward Computation of Dynamic Slices Using Reduced Ordered Binary Decision Diagrams.
Proceedings of the 26th International Conference on Software Engineering (ICSE 2004), 2004

Scalable Duplication Strategy with Bounded Availability of Processors.
Proceedings of the 10th International Conference on Parallel and Distributed Systems, 2004

2003
Fast Secure Processor for Inhibiting Software Piracy and Tampering.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Low cost instruction cache designs for tag comparison elimination.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Lightweight set buffer: low power data cache for multimedia application.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Precise Dynamic Slicing Algorithms.
Proceedings of the 25th International Conference on Software Engineering, 2003

Procedural Level Address Offset Assignment of DSP Applications with Loops.
Proceedings of the 32nd International Conference on Parallel Processing (ICPP 2003), 2003

Enabling Partial Cache Line Prefetching Through Data Compression.
Proceedings of the 32nd International Conference on Parallel Processing (ICPP 2003), 2003

Application-Specific Interconnection Network Design in Clustered DSP Processors.
Proceedings of the ISCA 16th International Conference on Parallel and Distributed Computing Systems, 2003

2002
Path Matching in Compressed Control Flow Trace.
Proceedings of the 2002 Data Compression Conference (DCC 2002), 2002

Data Compression Transformations for Dynamically Allocated Data Structures.
Proceedings of the Compiler Construction, 11th International Conference, 2002

A Representation for Bit Section Based Analysis and Optimization.
Proceedings of the Compiler Construction, 11th International Conference, 2002

Profile-Guided Compiler Optimizations.
Proceedings of the Compiler Design Handbook: Optimizations and Machine Code Generation, 2002

2001
Timestamped Whole Program Path Representation and its Applications.
Proceedings of the 2001 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2001

2000
Frequent value compression in data caches.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

Frequent Value Locality and Value-Centric Data Cache Design.
Proceedings of the ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000


  Loading...