Jun Yang

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

ModelShield: A Generic and Portable Framework Extension for Defending Bit-Flip based Adversarial Weight Attacks.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

IVcache: Defending Cache Side Channel Attacks via Invisible Accesses.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

An Adaptive Framework for Oversubscription Management in CPU-GPU Unified Memory.

[BibT_eX]

[DOI]

Debashis Ganguly

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Boosting the Performance of SSDs via Fully Exploiting the Plane Level Parallelism.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2020

Exploiting In-Memory Data Patterns for Performance Improvement on Crossbar Resistive Memory.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Dynamic and Proactive GPU Preemption Mechanism Using Checkpointing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Aging Capacitor Supported Cache Management Scheme for Solid-State Drives.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Leveraging partial-refresh for performance and lifetime improvement of 3D NAND flash memory in cyber-physical systems.

[BibT_eX]

[DOI]

J. Syst. Archit., 2020

Adaptive Page Migration for Irregular Data-intensive Applications under GPU Memory Oversubscription.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2020

Accelerating 3D Vertical Resistive Memories with Opportunistic Write Latency Reduction.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

ELP2IM: Efficient and Low Power Bitwise Operation Processing in DRAM.

[BibT_eX]

[DOI]

Xin Xin

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

SCA: A Secure CNN Accelerator for Both Training and Inference.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Reducing DRAM Access Latency via Helper Rows.

[BibT_eX]

[DOI]

Xin Xin

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Layer RBER Variation Aware Read Performance Optimization for 3D Flash Memories.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Enhancing Address Translations in Throughput Processors via Compression.

[BibT_eX]

[DOI]

Xulong Tang

Ziyu Zhang

Weizheng Xu

Mahmut Taylan Kandemir

Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019

Priority-Based PCIe Scheduling for Multi-Tenant Multi-GPU Systems.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2019

DIR: Dynamic Request Interleaving for Improving the Read Performance of Aged SSDs.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Non-Volatile Memory Systems and Applications Symposium, 2019

Parallel all the time: Plane Level Parallelism Exploration for High Performance SSDs.

[BibT_eX]

[DOI]

Proceedings of the 35th Symposium on Mass Storage Systems and Technologies, 2019

Constructing Large, Durable and Fast SSD System via Reprogramming 3D TLC Flash Memory.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

PageCmp: Bandwidth Efficient Page Deduplication through In-memory Page Comparison.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Interplay between hardware prefetcher and page eviction policy in CPU-GPU unified virtual memory.

[BibT_eX]

[DOI]

Proceedings of the 46th International Symposium on Computer Architecture, 2019

RFAcc: a 3D ReRAM associative array based random forest accelerator.

[BibT_eX]

[DOI]

Proceedings of the ACM International Conference on Supercomputing, 2019

ReNEW: Enhancing Lifetime for ReRAM Crossbar Based Neural Network Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

ROC: DRAM-based Processing with Reduced Operation Cycles.

[BibT_eX]

[DOI]

Xin Xin

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

H-ORAM: A Cacheable ORAM Interface for Efficient I/O Accesses.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Leveraging Approximate Data for Robust Flash Storage.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

LAcc: Exploiting Lookup Table-based Fast and Accurate Vector Multiplication in DRAM-based CNN Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A Framework for Memory Oversubscription Management in Graphics Processing Units.

[BibT_eX]

[DOI]

Chen Li

Rachata Ausavarungnirun

Christopher J. Rossbach

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

Boosting chipkill capability under retention-error induced reliability emergency.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

ApproxFTL: On the Performance and Lifetime Improvement of 3-D NAND Flash-Based SSDs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Process-Variation-Tolerant Method for Nanophotonic On-Chip Network.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2018

Initial Steps toward Making GPU a First-Class Computing Resource: Sharing and Resource Management.

[BibT_eX]

[DOI]

Proceedings of the 11th Workshop on General Purpose Processing using GPUs, 2018

Enabling Intra-Plane Parallel Block Erase in NAND Flash to Alleviate the Impact of Garbage Collection.

[BibT_eX]

[DOI]

Tyler Garrett

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

D-ORAM: Path-ORAM Delegation for Low Execution Interference on Cloud Servers with Untrusted Memory.

[BibT_eX]

[DOI]

Rujia Wang

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

ShadowGC: Cooperative garbage collection with multi-level buffer for performance improvement in NAND flash-based SSDs.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Wear leveling for crossbar resistive memory.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

DrAcc: a DRAM based accelerator for accurate CNN inference.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

PEP: proactive checkpointing for efficient preemption on GPUs.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

On the Restore Time Variations of Future DRAM Memory.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2017

Optimizing power efficiency for 3D stacked GPU-in-memory architecture.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

Decongest: Accelerating Super-Dense PCM Under Write Disturbance by Hot Page Remapping.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2017

Mitigating shift-based covert-channel attacks in racetrack last level caches.

[BibT_eX]

[DOI]

Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

Constructing fast and energy efficient 1TnR based ReRAM crossbar memory.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Quality of Service Support for Fine-Grained Sharing on GPUs.

[BibT_eX]

[DOI]

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Read Error Resilient MLC STT-MRAM Based Last Level Cache.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

AEP: An error-bearing neural network accelerator for energy efficiency and model protection.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Speeding up crossbar resistive memory by exploiting in-memory data patterns.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Towards warp-scheduler friendly STT-RAM/SRAM hybrid GPGPU register file design.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Cooperative Path-ORAM for Effective Memory Bandwidth Sharing in Server Settings.

[BibT_eX]

[DOI]

Rujia Wang

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

DrMP: Mixed Precision-Aware DRAM for High Performance Approximate and Precise Computing.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016

Simultaneous Multikernel: Fine-Grained Sharing of GPUs.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2016

AWARD: Approximation-aWAre Restore in Further Scaling DRAM.

[BibT_eX]

[DOI]

Proceedings of the Second International Symposium on Memory Systems, 2016

Restore truncation for performance improvement in future DRAM systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Simultaneous Multikernel GPU: Multi-tasking throughput processors via fine-grained sharing.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

ReadDuo: Constructing Reliable MLC Phase Change Memory through Fast and Robust Readout.

[BibT_eX]

[DOI]

Rujia Wang

Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2016

2015

Simple Virtual Channel Allocation for High-Throughput and High-Frequency On-Chip Routers.

[BibT_eX]

[DOI]

ACM Trans. Parallel Comput., 2015

Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM Technology.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

Transformer: Run-time reprogrammable heterogeneous architecture for transparent acceleration of dynamic workloads.

[BibT_eX]

[DOI]

Peilong Li

Yan Luo

J. Parallel Distributed Comput., 2015

SAWS: synchronization aware GPGPU warp scheduling for multiple independent warp schedulers.

[BibT_eX]

[DOI]

Jiwei Liu

Proceedings of the 48th International Symposium on Microarchitecture, 2015

Achieving Yield, Density and Performance Effective DRAM at Extreme Technology Sizes.

[BibT_eX]

[DOI]

Bruce R. Childers

Proceedings of the 2015 International Symposium on Memory Systems, 2015

GASOLIN: Global Arbitration for Streams of Data in Optical Links.

[BibT_eX]

[DOI]

Jiwei Liu

Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium, 2015

Exploit common source-line to construct energy efficient domain wall memory based caches.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

TriState-SET: Proactive SET for improved performance of MLC phase change memories.

[BibT_eX]

[DOI]

XianWei Zhang

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

DLB: Dynamic lane borrowing for improving bandwidth and performance in Hybrid Memory Cube.

[BibT_eX]

[DOI]

XianWei Zhang

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Exploiting DRAM restore time variations in deep sub-micron scaling.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Selective restore: an energy efficient read disturbance mitigation scheme for future STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

BandArb: mitigating the effects of thermal and process variations in silicon-photonic network.

[BibT_eX]

[DOI]

Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

SD-PCM: Constructing Reliable Super Dense Phase Change Memory under Write Disturbance.

[BibT_eX]

[DOI]

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014

Throughput Enhancement for Phase Change Memories.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Errata to "Process Variation-Aware Nonuniform Cache Management in a 3D Die-Stacked Multicore Processor".

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

A low power and reliable charge pump design for Phase Change Memories.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Mitigating Write Disturbance in Super-Dense Phase Change Memories.

[BibT_eX]

[DOI]

Lei Jiang

Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2014

2013

Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

Process Variation-Aware Nonuniform Cache Management in a 3D Die-Stacked Multicore Processor.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2013

A speculative arbiter design to enable high-frequency many-VC router in NoCs.

[BibT_eX]

[DOI]

Bo Zhao

Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

WoM-SET: Low power proactive-SET-based PCM write using WoM code.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

The design of sustainable wireless sensor network node using solar energy and phase change memory.

[BibT_eX]

[DOI]

Ping Zhou

Proceedings of the Design, Automation and Test in Europe, 2013

Low cost power failure protection for MLC NAND flash storage systems with PRAM/DRAM hybrid buffer.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory.

[BibT_eX]

[DOI]

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

ER: elastic RESET for low power and long endurance MLC based phase change memory.

[BibT_eX]

[DOI]

Lei Jiang

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Tolerating process variations in nanophotonic on-chip networks.

[BibT_eX]

[DOI]

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Channel borrowing: an energy-efficient nanophotonic crossbar architecture with light-weight arbitration.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Supercomputing, 2012

Improving write operations in MLC phase change memory.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Architecting a common-source-line array for bipolar non-volatile memory devices.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

SenGuard: Passive user identification on smartphones using multiple sensors.

[BibT_eX]

[DOI]

Proceedings of the IEEE 7th International Conference on Wireless and Mobile Computing, 2011

Enhancing phase change memory lifetime through fine-grained current regulation and voltage upscaling.

[BibT_eX]

[DOI]

Lei Jiang

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

A composite and scalable cache coherence protocol for large scale CMPs.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/IFIP International Conference on Dependable Systems and Networks, 2011

Proactive recovery for BTI in high-k SRAM cells.

[BibT_eX]

[DOI]

Lin Li

Proceedings of the Design, Automation and Test in Europe, 2011

MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache Replacement.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010

The design and evaluation of interleaved authentication for filtering false reports in multipath routing WSNs.

[BibT_eX]

[DOI]

Wirel. Networks, 2010

Thermal-Aware Task Scheduling for 3D Multicore Processors.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2010

Performance-aware thermal management via task scheduling.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2010

Phase-Change Technology and the Future of Main Memory.

[BibT_eX]

[DOI]

IEEE Micro, 2010

A low-cost memory remapping scheme for address bus protection.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2010

An authentication scheme for locating compromised sensor nodes in WSNs.

[BibT_eX]

[DOI]

J. Netw. Comput. Appl., 2010

Fine-grained QoS scheduling for PCM-based main memory systems.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Proactive NBTI mitigation for busy functional units in out-of-order microprocessors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Energy-efficient encoding techniques for off-chip data buses.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2009

Tunable and Energy Efficient Bus Encoding Techniques.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2009

Towards update-conscious compilation for energy-efficient code dissemination in WSNs.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2009

Supporting flexible streaming media protection through privacy-aware secure processors.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2009

Variation-tolerant non-uniform 3D cache management in die stacked multicore processor.

[BibT_eX]

[DOI]

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

A durable and energy efficient main memory using phase change memory technology.

[BibT_eX]

[DOI]

Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Energy reduction for STT-RAM using early write termination.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A low-radix and low-diameter 3D interconnection network design.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Frequent value compression in packet-based NoC architectures.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Dynamic Thermal Management through Task Scheduling.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

Towards energy-efficient code dissemination in wireless sensor networks.

[BibT_eX]

[DOI]

Weijia Li

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Thermal Management for 3D Processors via Task Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Parallel Processing, 2008

Adaptive Buffer Management for Efficient Code Dissemination in Multi-Application Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

2007

Efficient power modeling and software thermal sensing for runtime temperature monitoring.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

Conserving network processor power consumption by exploiting traffic variability.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2007

UCC: update-conscious compilation for energy efficiency in wireless sensor networks.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, 2007

Improving the reliability of on-chip data caches under process variations.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Computer Design, 2007

Program Mapping onto Network Processors by Recursive Bipartitioning and Refining.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

Fast Thermal Simulation for Runtime Temperature Tracking and Management.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Dynamic Authentication-Key Re-assignment for Reliable Report Delivery.

[BibT_eX]

[DOI]

Weijia Li

Proceedings of the IEEE 3rd International Conference on Mobile Adhoc and Sensor Systems, 2006

The interleaved authentication for filtering false reports in multipath routing based sensor networks.

[BibT_eX]

[DOI]

Hai Trong Vu

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Reduce Register Files Leakage Through Discharging Cells.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

InfoShield: a security architecture for protecting information usage in memory.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

Locating Compromised Sensor Nodes Through Incremental Hashing Authentication.

[BibT_eX]

[DOI]

Proceedings of the Distributed Computing in Sensor Systems, 2006

A systematic method for functional unit power estimation in microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Efficient Group KeyManagement with Tamper-resistant ISA Extensions.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

A low-cost memory remapping scheme for address bus protection.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005

Improving Memory Encryption Performance in Secure Processors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

Architectural support for protecting user privacy on trusted processors.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2005

A low energy cache design for multimedia applications exploiting set access locality.

[BibT_eX]

[DOI]

Jia Yu

J. Syst. Archit., 2005

Reducing I-cache energy of multimedia applications through low cost tag comparison elimination.

[BibT_eX]

[DOI]

J. Embed. Comput., 2005

Power Efficient Instruction Caches for Embedded Systems.

[BibT_eX]

[DOI]

Dinesh C. Suresh

Walid A. Najjar

Proceedings of the Embedded Computer Systems: Architectures, 2005

Supporting efficient query processing on compressed XML files.

[BibT_eX]

[DOI]

Proceedings of the 2005 ACM Symposium on Applied Computing (SAC), 2005

A tunable bus encoder for off-chip data buses.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Dynamic Co-allocation of Level One Caches.

[BibT_eX]

[DOI]

Proceedings of the Embedded Software and Systems, Second International Conference, 2005

VALVE: Variable Length Value Encoder for Off-Chip Data Buses..

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Efficient Thermal Simulation for Run-Time Temperature Tracking and Management.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Fast thermal simulation for architecture level dynamic thermal management.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

Enhancing Network Processor Simulation Speed with Statistical Input Sampling.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2005

Assertion-Based Design Exploration of DVS in Network Processor Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Low power network processor design using clock gating.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

2004

Frequent value encoding for low power data buses.

[BibT_eX]

[DOI]

Chuanjun Zhang

ACM Trans. Design Autom. Electr. Syst., 2004

NePSim: A Network Processor Simulator with a Power Evaluation Framework.

[BibT_eX]

[DOI]

IEEE Micro, 2004

Assertion-based power/performance analysis of network processor architectures.

[BibT_eX]

[DOI]

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Low Static-Power Frequent-Value Data Caches.

[BibT_eX]

[DOI]

Chuanjun Zhang

Frank Vahid

Proceedings of the 2004 Design, 2004

2003

A Way-Halting Cache for Low-Energy High-Performance Systems.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2003

Fast Secure Processor for Inhibiting Software Piracy and Tampering.

[BibT_eX]

[DOI]

Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Low cost instruction cache designs for tag comparison elimination.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Lightweight set buffer: low power data cache for multimedia application.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Procedural Level Address Offset Assignment of DSP Applications with Loops.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on Parallel Processing (ICPP 2003), 2003

FV-MSB: A Scheme for Reducing Transition Activity on Data Buses.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing - HiPC 2003, 10th International Conference, 2003

Power efficient encoding techniques for off-chip data buses.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Compilers, 2003

2002

Frequent value locality and its applications.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2002

Energy efficient frequent value data cache design.

[BibT_eX]

[DOI]

Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

2001

FV encoding for low-power data I/O.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Energy-efficient load and store reuse.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000

Frequent value compression in data caches.

[BibT_eX]

[DOI]

Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

Load Redundancy Removal through Instruction Reuse.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Conference on Parallel Processing, 2000

Frequent Value Locality and Value-Centric Data Cache Design.

[BibT_eX]

[DOI]