Anurag Pulincherry

According to our database, Anurag Pulincherry authored at least 5 papers between 2003 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

A Highly Integrated CMOS Analog Baseband Transceiver With 180 MSPS 13-bit Pipelined CMOS ADC and Dual 12-bit DACs.

Kush Gulati, Mark Peng, Anurag Pulincherry, Carlos E. Muñoz, Mike Lugin, Alex R. Bugeja, Jipeng Li, Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2006

2005

A time-delay jitter-insensitive continuous-time bandpass ΔΣ modulator architecture.

Anurag Pulincherry, Mike Hufford, Eric Naviasky, Un-Ku Moon

IEEE Trans. Circuits Syst. II Express Briefs, 2005

A highly-integrated CMOS analog baseband transceiver with 180MSPS 13b pipelined CMOS ADC and dual 12b DACs.

Kush Gulati, Mark Peng, Anurag Pulincherry, Carlos E. Muñoz, Mike Lugin, Alex R. Bugeja, Jipeng Li, Anantha P. Chandrakasan

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003

A behavioral modeling approach to the design of a low jitter clock source.

Gabriele Manganaro, Sung-Ung Kwak, SeongHwan Cho, Anurag Pulincherry

IEEE Trans. Circuits Syst. II Express Briefs, 2003

Continuous-time, frequency translating, bandpass delta-sigma modulator.

Anurag Pulincherry, Mike Hufford, Eric Naviasky, Un-Ku Moon

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003