Gabriele Manganaro

Orcid: 0000-0002-5957-6851

According to our database1, Gabriele Manganaro authored at least 37 papers between 1995 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2016, "For leadership in the design of high-speed converters".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.
IEEE J. Solid State Circuits, April, 2024

2023
Generalized Sampling-Based Multi-Channel Sampling of Signals Realized With Pure Delay Analog Filters and Digital FIR Reconstruction Filters.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

New Year Editorial 2023.
IEEE Open J. Circuits Syst., 2023

A 14b 16GS/s Time-Interleaving Oirect-RF Synthesis OAe with T-OEM Achieving -70dBc IM3 up to 7.8GHz in 7nm.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
Editorial: Where Are We Now and Where Do We Go From Here.
IEEE Open J. Circuits Syst., 2022

A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
Editorial on the Special Section on the 2021 IEEE International Symposium on Integrated Circuits and Systems.
IEEE Open J. Circuits Syst., 2021

New Year Editorial.
IEEE Open J. Circuits Syst., 2021

2020
Inaugural Issue of the IEEE Open Journal of Circuits and Systems: Welcome Note.
IEEE Open J. Circuits Syst., 2020

2018
In-situ nonlinear calibration of a RF signal chain.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Emerging data converter architectures and techniques.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology.
IEEE J. Solid State Circuits, 2017

2014
A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF.
IEEE J. Solid State Circuits, 2014

2013
Outgoing Editorial.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Progress update and a look ahead.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
Incoming Editorial.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Guest Editorial Special Issue on ISCAS 2011.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
Guest Editorial Special Issue on ISCAS 2010.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Guest Editorial Special Section on 2010 IEEE Custom Integrated Circuits Conference (CICC 2010).
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Advanced transmitters for wireless infrastructure.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
Guest Editorial Special Section on 2009 IEEE Custom Integrated Circuits Conference.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Guest Editorial Special Section on 2009 IEEE System-on-Chip Conference.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2008
A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC.
IEEE J. Solid State Circuits, 2008

40 MHz IF 1 MHz Bandwidth Two-Path Bandpass ΣΔ Modulator With 72 dB DR Consuming 16 mW.
IEEE J. Solid State Circuits, 2008

A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDAC.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
Two-path band-pass Δ∑ modulator with 40-MHz IF 72-dB DR at 1-MHz bandwidth consuming 16 mW.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2004
A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer.
IEEE J. Solid State Circuits, 2004

2003
A behavioral modeling approach to the design of a low jitter clock source.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

A dual 10b 200MSPS pipeline D/A converter with DLL-based clock synthesizer.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2001
An improved phase clock generator for interleaved and double-sampled switched-capacitor circuits.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
Nonlinear Computability Based on Chaos.
Int. J. Bifurc. Chaos, 2000

A triple 8b, 80MSPS 3.3 V graphics digitizer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1997
Cellular neural networks to explore complexity.
Soft Comput., 1997

1996
Generation of n-double scrolls via cellular neural networks.
Int. J. Circuit Theory Appl., 1996

1995
Complexity in an Industrial flyback converter.
J. Circuits Syst. Comput., 1995


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