Anushree Mahapatra

Orcid: 0000-0002-6035-6178

According to our database1, Anushree Mahapatra authored at least 9 papers between 2014 and 2023.

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Bibliography

2023
Fuzzing+Hardware Performance Counters-Based Detection of Algorithm Subversion Attacks on Postquantum Signature Schemes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

A Golden-Free Approach to Detect Trojans in COTS Multi-PCB Systems.
IEEE Micro, 2023

2022
Fuzzing+Hardware Performance Counters-Based Detection of Algorithm Subversion Attacks on Post-Quantum Signature Schemes.
CoRR, 2022

2021
Hardware Performance Counters: Ready-Made vs Tailor-Made.
ACM Trans. Embed. Comput. Syst., 2021

2019
Design space exploration of heterogeneous MPSoCs with variable number of hardware accelerators.
Microprocess. Microsystems, 2019

<i>VeriIntel2C</i>: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration.
Integr., 2019

Optimizing RTL to C Abstraction Methodologies to Improve HLS Design Space Exploration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Accelerating cycle-accurate system-level simulations through behavioral templates.
Integr., 2018

2014
S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis.
IEEE Embed. Syst. Lett., 2014


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