Anushree Mahapatra
Orcid: 0000-0002-6035-6178
According to our database1,
Anushree Mahapatra
authored at least 9 papers
between 2014 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
Fuzzing+Hardware Performance Counters-Based Detection of Algorithm Subversion Attacks on Postquantum Signature Schemes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
2022
Fuzzing+Hardware Performance Counters-Based Detection of Algorithm Subversion Attacks on Post-Quantum Signature Schemes.
CoRR, 2022
2021
ACM Trans. Embed. Comput. Syst., 2021
2019
Design space exploration of heterogeneous MPSoCs with variable number of hardware accelerators.
Microprocess. Microsystems, 2019
<i>VeriIntel2C</i>: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration.
Integr., 2019
Optimizing RTL to C Abstraction Methodologies to Improve HLS Design Space Exploration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Integr., 2018
2014
IEEE Embed. Syst. Lett., 2014