Arash Saifhashemi

According to our database1, Arash Saifhashemi authored at least 10 papers between 2003 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
Reconditioning: A Framework for Automatic Power Optimization of QDI Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2015
Logical equivalence checking of asynchronous circuits using commercial tools.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

Reconditioning: Automatic Power Optimization of QDI Circuits.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

2012
Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

2011
SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces.
Proceedings of the 33th Communicating Process Architectures Conference, 2011

2007
Notes On Pulse Signaling.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

2005
High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog.
Proceedings of the 28th Communicating Process Architectures Conference, 2005

MILO: personal robot platform.
Proceedings of the 2005 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2005

2003
Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction.
Proceedings of the 40th Design Automation Conference, 2003


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