William Koven

According to our database1, William Koven authored at least 8 papers between 2013 and 2024.

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Bibliography

2024
11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries.
Proceedings of the 28th IEEE International Symposium on Asynchronous Circuits and Systems, 2023

2022
System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2017
Sharp - A Resilient Asynchronous Template.
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

2016
Adding Conditionality to Resilient Bundled-Data Designs.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2014
Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

2013
Implementation of a 64-bit Jackson adder.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

Comparison of parallelized radix-2 and radix-4 scalable Montgomery multipliers.
Proceedings of the 2013 Asilomar Conference on Signals, 2013


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