Arijit Banerjee

Affiliations:
  • University of Virginia, Charlottesville, VA, USA


According to our database1, Arijit Banerjee authored at least 5 papers between 2014 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

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Online presence:

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Bibliography

2019
A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2018
Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

2017
A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2015
A 130nm canary SRAM for SRAM dynamic write VMIN tracking across voltage, frequency, and temperature variations.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014


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