Harsh N. Patel

According to our database1, Harsh N. Patel authored at least 8 papers between 2016 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


A 1.02 μW Battery-Less, Continuous Sensing and Post-Processing SiP for Wearable Applications.
IEEE Trans. Biomed. Circuits Syst., 2019

A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Subthreshold SRAM: Challenges, design decisions, and solutions.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Soft errors: Reliability challenges in energy-constrained ULP body sensor networks applications.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Improving Reliability and Energy Requirements of Memory in Body Sensor Networks.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Optimizing SRAM bitcell reliability and energy for IoT applications.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016