Ningxi Liu

According to our database1, Ningxi Liu authored at least 15 papers between 2013 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
30.1 A Temperature-Robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X-Band.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
Adaptive fault-tolerant control for a joint flexible manipulator based on dynamic surface.
Trans. Inst. Meas. Control, 2019

A 1.02 μW Battery-Less, Continuous Sensing and Post-Processing SiP for Wearable Applications.
IEEE Trans. Biomed. Circuits Syst., 2019

Interference Robust Detector-First Near-Zero Power Wake-Up Receiver.
IEEE J. Solid State Circuits, 2019

A 2.5 ppm/°C 1.05-MHz Relaxation Oscillator With Dynamic Frequency-Error Compensation and Fast Start-Up Time.
IEEE J. Solid State Circuits, 2019

A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
A -76dBm 7.4nW wakeup radio with automatic offset compensation.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-up Time.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017
A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Design Optimization of Register File Throughput and Energy Using a Virtual Prototyping (ViPro) Tool.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2014
Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

2013
Low-power high-yield SRAM design with VSS adaptive boosting and BL capacitance variation sensing.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Novel operation scheme and technological optimization for 1T bulk capacitor-less DRAM.
Proceedings of the IEEE 10th International Conference on ASIC, 2013


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