Benton H. Calhoun

According to our database1, Benton H. Calhoun authored at least 124 papers between 2003 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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On csauthors.net:

Bibliography

2019
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS.
IEEE Trans. on Circuits and Systems, 2019

A 1.02 μW Battery-Less, Continuous Sensing and Post-Processing SiP for Wearable Applications.
IEEE Trans. Biomed. Circuits and Systems, 2019

Interference Robust Detector-First Near-Zero Power Wake-Up Receiver.
J. Solid-State Circuits, 2019

A 2.5 ppm/°C 1.05-MHz Relaxation Oscillator With Dynamic Frequency-Error Compensation and Fast Start-Up Time.
J. Solid-State Circuits, 2019

Analysis and Design of an Ultra-Low-Power Bluetooth Low-Energy Transmitter With Ring Oscillator-Based ADPLL and 4 $\times$ Frequency Edge Combiner.
J. Solid-State Circuits, 2019

Enhanced Interference Rejection Bluetooth Low-Energy Back-Channel Receiver With LO Frequency Hopping.
J. Solid-State Circuits, 2019

A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications.
Proceedings of the 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, 2019

A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier and Integrated MPPT Achieving 417% Energy-Extraction Improvement and 97% Tracking Efficiency.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 745pA Hybrid Asynchronous Binary-Searching and Synchronous Linear-Searching Digital LDO with 3.8×105 Dynamic Load Range, 99.99% Current Efficiency, and 2mV Output Voltage Ripple.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A Low Power Bluetooth Low-Energy Transmitter with a 10.5nJ Startup-Energy Crystal Oscillator.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A 640 pW 22 pJ/sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25°C Resolution.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A -76dBm 7.4nW wakeup radio with automatic offset compensation.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Lighting IoT Test Environment (LITE) Platform: Evaluating Light-Powered, Energy HarvestingEmbedded Systems.
Proceedings of the 2018 Global Internet of Things Summit, 2018

FGC: A Tool-flow for Generating and Configuring Custom FPGAs(Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-up Time.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017
Infrastructure Circuits for Lifetime Improvement of Ultra-Low Power IoT Devices.
IEEE Trans. on Circuits and Systems, 2017

Modeling trans-threshold correlations for reducing functional test time in ultra-low power systems.
Proceedings of the IEEE International Test Conference, 2017

Soft errors: Reliability challenges in energy-constrained ULP body sensor networks applications.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

FAR: A 4.12μW ferro-electric auto-recovery for battery-less BSN SoCs.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

A 71% efficient energy harvesting and power management unit for sub-μW power biomedical applications.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

A 3.77 nW, 11.4 fJ/b/mm link for reliable wireline communication in ultra-low power on-body sensor networks.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
A 1.5 nW, 32.768 kHz XTAL Oscillator Operational From a 0.3 V Supply.
J. Solid-State Circuits, 2016

Improving Reliability and Energy Requirements of Memory in Body Sensor Networks.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Design Optimization of Register File Throughput and Energy Using a Virtual Prototyping (ViPro) Tool.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

26.8 A 236nW -56.5dBm-sensitivity bluetooth low-energy wakeup receiver with energy harvesting in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A 1.3µW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applications.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Optimizing SRAM bitcell reliability and energy for IoT applications.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Exploring circuit robustness to power supply variation in low-voltage latch and register-based digital systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An energy-efficient near/sub-threshold FPGA interconnect architecture using dynamic voltage scaling and power-gating.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2015
Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization.
IEEE Trans. VLSI Syst., 2015

A 6.45 μW Self-Powered SoC With Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems.
IEEE Trans. Biomed. Circuits and Systems, 2015

Flexible Technologies for Self-Powered Wearable Health and Environmental Sensing.
Proceedings of the IEEE, 2015

A 10 mV-Input Boost Converter With Inductor Peak Current Control and Zero Detection for Thermoelectric and Solar Energy Harvesting With 220 mV Cold-Start and -14.5 dBm, 915 MHz RF Kick-Start.
J. Solid-State Circuits, 2015

5.4 A 32nW bandgap reference voltage operational from 0.5V supply for ultra-low power systems.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

21.3 A 6.45μW self-powered IoT SoC with integrated energy-harvesting power management and ULP asymmetric radios.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Stack based sense amplifier designs for reducing input-referred offset.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

A 0.38 pj/bit 1.24 nW chip-to-chip serial link for ultra-low power systems.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Error-energy analysis of hardware logarithmic approximation methods for low power applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Ultra-low power wireless SoCs enabling a batteryless IoT.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Using island-style bi-directional intra-CLB routing in low-power FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

A 130nm canary SRAM for SRAM dynamic write VMIN tracking across voltage, frequency, and temperature variations.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

Self-powered wearable sensor platforms for wellness.
Proceedings of the 2015 International Conference on Compilers, 2015

2014
A 32 b 90 nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation From Sub-Threshold to High Performance.
J. Solid-State Circuits, 2014

Pipelined Non-strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

A 1.2µW SIMO energy harvesting and power management unit with constant peak inductor current control achieving 83-92% efficiency across wide input and output voltages.
Proceedings of the Symposium on VLSI Circuits, 2014

Fast, accurate variation-aware path timing computation for sub-threshold circuits.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

A digital dynamic write margin sensor for low power read/write operations in 28nm SRAM.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Modeling SRAM dynamic VMIN.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

A 10mV-input boost converter with inductor peak current control and zero detection for thermoelectric energy harvesting.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A Batteryless 19 µW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications.
J. Solid-State Circuits, 2013

A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Circuit optimizations to minimize energy in the global interconnect of a low-power-FPGA (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN.
Proceedings of the Design, Automation and Test in Europe, 2013

Flexible on-chip power delivery for energy efficient heterogeneous systems.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Tracking On-Chip Age Using Distributed, Embedded Sensors.
IEEE Trans. VLSI Syst., 2012

Nonrandom Device Mismatch Considerations in Nanoscale SRAM.
IEEE Trans. VLSI Syst., 2012

A Programmable 34 nW/Channel Sub-Threshold Signal Band Power Extractor on a Body Sensor Node SoC.
IEEE Trans. on Circuits and Systems, 2012

Body Sensor Networks: A Holistic Approach From Silicon to Users.
Proceedings of the IEEE, 2012

Guest Editorial Emerging Circuits and Systems Techniques for Ultra-Low Power Body Sensor Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

A batteryless 19μW MICS/ISM-band energy harvesting body area sensor node SoC.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A charge pump based receiver circuit for voltage scaled interconnect.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

A programmable resistive power grid for post-fabrication flexibility and energy tradeoffs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Optimal power switch design for dynamic voltage scaling from high performance to subthreshold operation.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

A 150nW, 5ppm/o C, 100kHz On-Chip clock source for ultra low power SoCs.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A custom processor for node and power management of a battery-less body sensor node in 130nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
An Enhanced Canary-Based System With BIST for SRAM Standby Power Reduction.
IEEE Trans. VLSI Syst., 2011

Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations.
IEEE Trans. VLSI Syst., 2011

5T SRAM With Asymmetric Sizing for Improved Read Stability.
J. Solid-State Circuits, 2011

New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Stepped Supply Voltage Switching for energy constrained systems.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

An analytical model for performance yield of nanoscale SRAM accounting for the sense amplifier strobe signal.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Dynamic write limited minimum operating voltage for nanoscale SRAMs.
Proceedings of the Design, Automation and Test in Europe, 2011

Reducing the cost of redundant execution in safety-critical systems using relaxed dedication.
Proceedings of the Design, Automation and Test in Europe, 2011

A 90nm data flow processor demonstrating fine grained DVS for energy efficient operation from 0.25V to 1.2V.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Cost-effective safety and fault localization using distributed temporal redundancy.
Proceedings of the 14th International Conference on Compilers, 2011

2010
An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS.
IEEE Trans. on Circuits and Systems, 2010

Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Flexible Circuits and Architectures for Ultralow Power.
Proceedings of the IEEE, 2010

Can Subthreshold and Near-Threshold Circuits Go Mainstream?
IEEE Micro, 2010

Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Limits of bias based assist methods in nano-scale 6T SRAM.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

SRAM-based NBTI/PBTI sensor system design.
Proceedings of the 47th Design Automation Conference, 2010

Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers.
Proceedings of the 47th Design Automation Conference, 2010

Improving SRAM Vmin and yield by using variation-aware BTI stress.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Body Area Sensor Networks: Challenges and Opportunities.
IEEE Computer, 2009

Serial sub-threshold circuits for ultra-low-power systems.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

A 2.6 µW sub-threshold mixed-signal ECG SoC.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Sub-threshold Circuit Design with Shrinking CMOS Devices.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Sub-threshold Operation and Cross-hierarchy Design for Ultra Low Power Wearable Sensors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design.
Proceedings of the 27th International Conference on Computer Design, 2009

A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes.
Proceedings of the 27th International Conference on Computer Design, 2009

Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Mobile health monitoring through biotelemetry.
Proceedings of the 4th International ICST Conference on Body Area Networks, 2009

2008
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS.
Proceedings of the IEEE, 2008

Techniques to Extend Canary-Based Standby VDD Scaling for SRAMs to 45 nm and Beyond.
J. Solid-State Circuits, 2008

Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Analyzing static and dynamic write margin for nanometer SRAMs.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Power switch characterization for fine-grained dynamic voltage scaling.
Proceedings of the 26th International Conference on Computer Design, 2008

2007
A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation.
J. Solid-State Circuits, 2007

Analyzing and modeling process balance for sub-threshold circuit design.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Sub-threshold Design for Ultra Low-Power Systems
Series on Integrated Circuits and Systems, Springer, ISBN: 978-0-387-34501-7, 2006

Sub-threshold design: the challenges of minimizing circuit energy.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

2005
Low energy digital circuit design using sub-threshold operation.
PhD thesis, 2005

Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes.
IEEE Trans. Computers, 2005

2004
Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks.
VLSI Signal Processing, 2004

Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Characterizing and modeling minimum energy operation for subthreshold circuits.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Device sizing for minimum energy operation in subthreshold circuits.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Design methodology for fine-grained leakage control in MTCMOS.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Power-aware architectures and circuits for FPGA-based signal processing.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003


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