Arthur Tuminaro

According to our database, Arthur Tuminaro authored at least 3 papers between 1997 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane.

Rajiv V. Joshi, Rouwaida Kanj, Anthony Pelella, Arthur Tuminaro, Yuen H. Chan

IEEE Des. Test Comput., 2010

2005

A 8Kb domino read SRAM with hit logic and parity checker.

Antonio Pelella, Arthur Tuminaro, Ryan T. Freese, Yuen H. Chan

Proceedings of the 31st European Solid-State Circuits Conference, 2005

1997

A 400MHz, 144Kb CMOS ROM Macro for an IBM S/390-Class Microprocessor.

Arthur Tuminaro

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997