Ata Khorami

Orcid: 0000-0002-4066-1685

Affiliations:
  • Sharif University of Technology, Tehran, Iran


According to our database1, Ata Khorami authored at least 21 papers between 2015 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
ST-CAC: a low-cost crosstalk avoidance coding mechanism based on three-valued numerical system.
J. Supercomput., 2021

2020
A low-power low-offset charge-sharing technique for double-tail comparators.
Microelectron. J., 2020

Energy consumption analysis of the stepwise adiabatic circuits.
Microelectron. J., 2020

2019
A low-power dynamic comparator for low-offset applications.
Integr., 2019

A Contention-free, Static, Single-phase Flip-Flop for Low Data Activity Applications.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

An Ultra Low-power Low-offset Double-tail Comparator.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

2018
A Low-Power High-Speed Comparator for Precise Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Design of low power comparator-reduced hybrid ADC.
Microelectron. J., 2018

A low-power technique for high-resolution dynamic comparators.
Int. J. Circuit Theory Appl., 2018

2017
An Efficient Fast Switching Procedure for Stepwise Capacitor Chargers.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Excess power elimination in high-resolution dynamic comparators.
Microelectron. J., 2017

An ultra low-power digital to analog converter for SAR ADCs.
Proceedings of the 29th International Conference on Microelectronics, 2017

2016
General Characterization Method and a Fast Load-Charge-Preserving Switching Procedure for the Stepwise Adiabatic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

An accurate low-power DAC for SAR ADCs.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

A high-speed method of dynamic comparators for SAR analog to digital converters.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

A wide dynamic range low power 2× time amplifier using current subtraction scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A low-power high-speed comparator for analog to digital converters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Elimination of the effect of bottom-plate capacitors in C-2C DAC using a layout technique.
Microelectron. J., 2015

Analysis of the effects of clock imperfections in N-path filters.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Zero-power mismatch-independent Digital to Analog converter.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

A four bit low power 165MS/s flash-SAR ADC for sigma-delta ADC application.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015


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