Mohammad Sharifkhani

CoRR, 2022

2020

Compressed Domain Moving Object Detection Based on CRF.

[BibT_eX]

[DOI]

Mohammad Sadegh Alizadeh

IEEE Trans. Circuits Syst. Video Technol., 2020

Yield constrained automated design algorithm for power optimized pipeline ADC.

[BibT_eX]

[DOI]

Vala Sadrafshari

Shamin Sadrafshari

Integr., 2020

2019

A low-power dynamic comparator for low-offset applications.

[BibT_eX]

[DOI]

Integr., 2019

A Contention-free, Static, Single-phase Flip-Flop for Low Data Activity Applications.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

An Ultra Low-power Low-offset Double-tail Comparator.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

2018

A Low-Power High-Speed Comparator for Precise Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Temperature Compensation in CMOS Peaking Current References.

[BibT_eX]

[DOI]

Siavash Kananian

Amir M. Sodagar

IEEE Trans. Circuits Syst. II Express Briefs, 2018

A low-power technique for high-resolution dynamic comparators.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2018

JVET Encoder Complexity Analysis.

[BibT_eX]

[DOI]

Amir Ahmad Mohammadi

Mohammad Sadegh Alizadeh

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Time-Interleaved 2b/Cycle SAR ADC with Background Offset Calibration.

[BibT_eX]

[DOI]

Shahaboddin Ghajari

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

An Efficient Fast Switching Procedure for Stepwise Capacitor Chargers.

[BibT_eX]

[DOI]

Mohammadreza Ghaderi Karkani

IEEE Trans. Very Large Scale Integr. Syst., 2017

Analysis and Design of Power Harvesting Circuits for Ultra-Low Power Applications.

[BibT_eX]

[DOI]

Ali Asghar Razavi Haeri

Mahmoud Kamarei

Ali Fotowat-Ahmady

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Excess power elimination in high-resolution dynamic comparators.

[BibT_eX]

[DOI]

Microelectron. J., 2017

A low-power temperature-compensated CMOS peaking current reference in subthreshold region.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An ultra low-power digital to analog converter for SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on Microelectronics, 2017

2016

General Characterization Method and a Fast Load-Charge-Preserving Switching Procedure for the Stepwise Adiabatic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A Low-Latency QRD-RLS Architecture for High-Throughput Adaptive Applications.

[BibT_eX]

[DOI]

Mohammad Sadegh Alizadeh

Javad Bagherzadeh

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Ultra-low power current mode all- MOS ASK demodulator for radio frequency identification applications.

[BibT_eX]

[DOI]

Narges Mousavi

Mohsen Jalali

IET Circuits Devices Syst., 2016

An accurate low-power DAC for SAR ADCs.

[BibT_eX]

[DOI]

Seyed Behnam Yazdani

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

A high-speed method of dynamic comparators for SAR analog to digital converters.

[BibT_eX]

[DOI]

Seyed Mohammadreza Fatemi

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

2015

A Unified Solution for Super-Regenerative Systems With Application to Correlator-Based UWB Transceivers.

[BibT_eX]

[DOI]

Ali Fotowat-Ahmady

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Elimination of the effect of bottom-plate capacitors in C-2C DAC using a layout technique.

[BibT_eX]

[DOI]

Microelectron. J., 2015

Bandwidth enhancement of planar EBG structure using dissipative edge termination.

[BibT_eX]

[DOI]

Ali Sadr

Nasser Masoumi

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Zero-power mismatch-independent Digital to Analog converter.

[BibT_eX]

[DOI]

Ali Nikoofard

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Wireless interfacing to cortical neural recording implants using 4-FSK modulation scheme.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014

Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell.

[BibT_eX]

[DOI]

Roghayeh Saeidi

Khosrow Hajsadeghi

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A Subthreshold Symmetric SRAM Cell With High Read Stability.

[BibT_eX]

[DOI]

Roghayeh Saeidi

Khosrow Hajsadeghi

IEEE Trans. Circuits Syst. II Express Briefs, 2014

A low-power low-offset dynamic comparator for analog to digital converters.

[BibT_eX]

[DOI]

Mohsen Hassanpourghadi

Milad Zamani

Microelectron. J., 2014

An auto-calibrated, dual-mode SRAM macro using a hybrid offset-cancelled sense amplifier.

[BibT_eX]

[DOI]

Hourieh Attarzadeh

Microelectron. J., 2014

An efficient high-throughput LSI architecture for a synchronization block applied to real-time optical OFDM systems.

[BibT_eX]

[DOI]

Reza Ghanaatian

Mahdi Shabany

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A low-power 10-Bit 40-MS/s pipeline ADC using extended capacitor sharing.

[BibT_eX]

[DOI]

Hani Esmaeelzadeh

Mahdi Shabany

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 3-D inductive powering approach dedicated to implantable/wearable biomedical microsystems.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013

Fast Static Characterization of Residual-Based ADCs.

[BibT_eX]

[DOI]

Mohsen Hassanpourghadi

IEEE Trans. Circuits Syst. II Express Briefs, 2013

A 4-Bit, 1.6 GS/s Low Power Flash ADC, Based on Offset Calibration and Segmentation.

[BibT_eX]

[DOI]

Mohammad Chahardori

Sirus Sadughi

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Step response analysis of third order OpAmps With slew-rate.

[BibT_eX]

[DOI]

Mohsen Hassanpourghadi

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

A low power 1.2 GS/s 4-bit flash ADC in 0.18 µm CMOS.

[BibT_eX]

[DOI]

Mohammad Chahardori

Sirus Sadughi

Proceedings of the East-West Design & Test Symposium, 2013

A 10MHz CTDSM with differential VCO-based quantizer in 90nm.

[BibT_eX]

[DOI]

Bahman Yousefzadeh

Ali Hajian

Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

2011

A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

A sub 1 V high PSRR CMOS bandgap voltage reference.

[BibT_eX]

[DOI]

Mohammad Chahardori

Seyed Mojtaba Atarodi

Microelectron. J., 2011

A subthreshold dynamic read SRAM (DRSRAM) based on dynamic stability criteria.

[BibT_eX]

[DOI]

Roghayeh Saeidi

Khosrow Hajsadeghi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Implementation of a cost efficient SSL based on an Angular beamformer SRP-PHAT.

[BibT_eX]

[DOI]

Hamid R. Zarghi

Iman Gholampour

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

An audio band low voltage CT-ΔΣ modulator with VCO-based quantizer.

[BibT_eX]

[DOI]

Bahman Yousefzadeh

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

CMOS-compatible structure for voltage-mode multiple-valued logic circuits.

[BibT_eX]

[DOI]

Amir M. Sodagar

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

A low power 1-V 10-bit 40-MS/s pipeline ADC.

[BibT_eX]

[DOI]

Mohsen Hashemi

Mohammad Gholami

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010

A scalable offset-cancelled current/voltage sense amplifier.

[BibT_eX]

[DOI]

Hourieh Attarzadeh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Modeling of DLL-based frequency multiplier in time and frequency domain with Matlab Simulink.

[BibT_eX]

[DOI]

Mohammad Gholami

Saeed Saeedi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 µm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

SRAM Cell Stability: A Dynamic Perspective.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

2008

Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

Segmented Virtual Ground Architecture for Low-Power Embedded SRAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Dynamic Data Stability in Low-power SRAM Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

A low power SRAM architecture based on segmented virtual grounding.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

A phase-domain 2nd-order continuous time Delta-Sigma-modulator for frequency digitization.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Phase-Domain Continuous-Time 2<sup>nd</sup>-Order ΔΣ Frequency Digitizer.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2004

A frequency digitizer based on the continuous time phase domain noise shaping.

[BibT_eX]

[DOI]