Banit Agrawal

According to our database, Banit Agrawal authored at least 25 papers between 2003 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

Supporting Massive DLRM Inference through Software Defined Memory.

Ehsan K. Ardestani, Changkyu Kim, Seung Jae Lee, Luoshang Pan, Jens Axboe, Valmiki Rampersad, Banit Agrawal, Fuxun Yu, Ansha Yu, Trung Le, Hector Yuen, Dheevatsa Mudigere, Shishir Juluri, Akshat Nanda, Manoj Wodekar, Krishnakumar Nair, Maxim Naumov, Chris Petersen, Mikhail Smelyanskiy, Vijay Rao

Proceedings of the 42nd IEEE International Conference on Distributed Computing Systems, 2022

2021

Supporting Massive DLRM Inference Through Software Defined Memory.

Ehsan K. Ardestani, Changkyu Kim, Seung Jae Lee, Luoshang Pan, Valmiki Rampersad, Jens Axboe, Banit Agrawal, Fuxun Yu, Ansha Yu, Trung Le, Hector Yuen, Shishir Juluri, Akshat Nanda, Manoj Wodekar, Dheevatsa Mudigere, Krishnakumar Nair, Maxim Naumov, Chris Peterson, Mikhail Smelyanskiy, Vijay Rao

CoRR, 2021

2014

Benchmarking a virtualization platform.

Vijayaraghavan Soundararajan, Banit Agrawal, Bruce Herndon, Priya Sethuraman, H. Reza Taheri

Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

2012

Dataflow Tomography: Information Flow Tracking For Understanding and Visualizing Full Systems.

Bita Mazloom, Shashidhar Mysore, Mohit Tiwari, Banit Agrawal, Timothy Sherwood

ACM Trans. Archit. Code Optim., 2012

2009

High-bandwidth network memory system through virtual pipelines.

Banit Agrawal, Timothy Sherwood

IEEE/ACM Trans. Netw., 2009

Energy-efficient encoding techniques for off-chip data buses.

Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar

ACM Trans. Embed. Comput. Syst., 2009

Tunable and Energy Efficient Bus Encoding Techniques.

Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar

IEEE Trans. Computers, 2009

2008

Ternary CAM Power and Delay Model: Extensions and Uses.

Banit Agrawal, Timothy Sherwood

IEEE Trans. Very Large Scale Integr. Syst., 2008

Formulating and implementing profiling over adaptive ranges.

Shashidhar Mysore, Banit Agrawal, Rodolfo Neuber, Timothy Sherwood, Nisheeth Shrivastava, Subhash Suri

ACM Trans. Archit. Code Optim., 2008

Exploring the Processor and ISA Design for Wireless Sensor Network Applications.

Shashidhar Mysore, Banit Agrawal, Frederic T. Chong, Timothy Sherwood

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation.

Banit Agrawal, Timothy Sherwood, Chulho Shin, Simon Yoon

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags.

Mohit Tiwari, Banit Agrawal, Shashidhar Mysore, Jonathan Valamehr, Timothy Sherwood

Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Understanding and visualizing full systems with data flow tomography.

Shashidhar Mysore, Bita Mazloom, Banit Agrawal, Timothy Sherwood

Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008

2007

3D Integration for Introspection.

Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood

IEEE Micro, 2007

2006

Virtually Pipelined Network Memory.

Banit Agrawal, Timothy Sherwood

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Modeling TCAM power for next generation network devices.

Banit Agrawal, Timothy Sherwood

Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006

Guiding Architectural SRAM Models.

Banit Agrawal, Timothy Sherwood

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy.

Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee

Proceedings of the 43rd Design Automation Conference, 2006

Profiling over Adaptive Ranges.

Shashidhar Mysore, Banit Agrawal, Timothy Sherwood, Nisheeth Shrivastava, Subhash Suri

Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006

Introspective 3D chips.

Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood

Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

2005

A tunable bus encoder for off-chip data buses.

Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

VALVE: Variable Length Value Encoder for Off-Chip Data Buses..

Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, Jun Yang

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Controlling spam Emails at the routers.

Banit Agrawal, Nitin Kumar, Mart L. Molle

Proceedings of IEEE International Conference on Communications, 2005

2003

FV-MSB: A Scheme for Reducing Transition Activity on Data Buses.

Dinesh C. Suresh, Jun Yang, Chuanjun Zhang, Banit Agrawal, Walid A. Najjar

Proceedings of the High Performance Computing - HiPC 2003, 10th International Conference, 2003

Power efficient encoding techniques for off-chip data buses.

Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar, Laxmi N. Bhuyan

Proceedings of the International Conference on Compilers, 2003