Navin Srivastava

According to our database, Navin Srivastava authored at least 14 papers between 2005 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates.

Chuan Xu, Navin Srivastava, Roberto Suaya, Kaustav Banerjee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2010

Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060].

Navin Srivastava, Chuan Xu, Roberto Suaya, Kaustav Banerjee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate.

Navin Srivastava, Roberto Suaya, Kaustav Banerjee

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate.

Navin Srivastava, Roberto Suaya, Kaustav Banerjee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2008

High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate.

Navin Srivastava, Roberto Suaya, Kaustav Banerjee

Proceedings of the Design, Automation and Test in Europe, 2008

2007

3D Integration for Introspection.

Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood

IEEE Micro, 2007

2006

Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections?

Kaustav Banerjee, Sungjun Im, Navin Srivastava

Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy.

Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee

Proceedings of the 43rd Design Automation Conference, 2006

Are carbon nanotubes the future of VLSI interconnections?

Kaustav Banerjee, Navin Srivastava

Proceedings of the 43rd Design Automation Conference, 2006

Introspective 3D chips.

Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood

Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems.

Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits.

Navin Srivastava, Xiaoning Qi, Kaustav Banerjee

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs.

Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Performance analysis of carbon nanotube interconnects for VLSI applications.

Navin Srivastava, Kaustav Banerjee

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005