Chuanjun Zhang

Orcid: 0009-0005-2233-6781

According to our database1, Chuanjun Zhang authored at least 40 papers between 2002 and 2023.

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Bibliography

2023
On (p,q)-Fibonacci and (p,q)-Lucas Polynomials Associated with Changhee Numbers and Their Properties.
Symmetry, March, 2023

Constant Time Calculation of the Metric Dimension of the Join of Path Graphs.
Symmetry, February, 2023

Study of Raising Students Level of Geometric Understanding with the Aid of Technology.
Proceedings of the 7th International Conference on Education and Multimedia Technology, 2023

2022
Design of Teaching Model for Intuitive Imagination Development Supported by NetPad.
Proceedings of the Computer Science and Education - 17th International Conference, 2022

2021
Approximate Computation on Commodity Computers through Bit-Serial Processing.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021

Design and Implementation of a 3D Dynamic Geometric Global Coordinate System.
Proceedings of the 16th International Conference on Computer Science & Education, 2021

A Comparative Study of Solving the Surface Area of Solid Figures in Dynamic Geometry System.
Proceedings of the 16th International Conference on Computer Science & Education, 2021

2020
DSCALE_mod16: A Model for Disaggregating Microwave Satellite Soil Moisture with Land Surface Evapotranspiration Products and Gridded Meteorological Data.
Remote. Sens., 2020

The 3D Projection Function on NetPad.
Proceedings of the 15th International Conference on Computer Science & Education, 2020

2016
The Beauty of Geometry: A touch-operation-based DGS for mathematics education.
Proceedings of the 11th International Conference on Computer Science & Education, 2016

2014
Exploiting natural redundancy in visual information.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

A task-oriented vision system.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013
EMERALD: Characterization of emerging applications and algorithms for low-power devices.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

WoM-SET: Low power proactive-SET-based PCM write using WoM code.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Dynamic bandwidth adaptation using recognition accuracy prediction through pre-classification for embedded vision systems.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Accelerators for biologically-inspired attention and recognition.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2010
A tag-based cache replacement.
Proceedings of the 28th International Conference on Computer Design, 2010

2009
Divide-and-conquer: a bubble replacement for low level caches.
Proceedings of the 23rd international conference on Supercomputing, 2009

2008
Reducing cache misses through programmable decoders.
ACM Trans. Archit. Code Optim., 2008

Two dimensional highly associative level-two cache design.
Proceedings of the 26th International Conference on Computer Design, 2008

2006
Balanced instruction cache: reducing conflict misses of direct-mapped caches through balanced subarray accesses.
IEEE Comput. Archit. Lett., 2006

Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A Low Power Highly Associative Cache for Embedded Systems.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Reduce Register Files Leakage Through Discharging Cells.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2005
A highly configurable cache for low energy embedded systems.
ACM Trans. Embed. Comput. Syst., 2005

Dynamic Co-allocation of Level One Caches.
Proceedings of the Embedded Software and Systems, Second International Conference, 2005

An efficient direct mapped instruction cache for application-specific embedded systems.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004
Frequent value encoding for low power data buses.
ACM Trans. Design Autom. Electr. Syst., 2004

A self-tuning cache architecture for embedded systems.
ACM Trans. Embed. Comput. Syst., 2004

Low Static-Power Frequent-Value Data Caches.
Proceedings of the 2004 Design, 2004

Using a Victim Buffer in an Application-Specific Memory Hierarchy.
Proceedings of the 2004 Design, 2004

Tuning Caches to Applications for Low-Energy Embedded Systems.
Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003
Highly configurable platforms for embedded computing systems.
Microelectron. J., 2003

A Way-Halting Cache for Low-Energy High-Performance Systems.
IEEE Comput. Archit. Lett., 2003

Cache Configuration Exploration on Prototyping Platforms.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

Energy Benefits of a Configurable Line Size Cache for Embedded Systems.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

A Highly-Configurable Cache Architecture for Embedded Systems.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

FV-MSB: A Scheme for Reducing Transition Activity on Data Buses.
Proceedings of the High Performance Computing - HiPC 2003, 10th International Conference, 2003

2002
A power-configurable bus for embedded systems.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002


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