Timothy Sherwood

According to our database1, Timothy Sherwood
  • authored at least 126 papers between 1998 and 2017.
  • has a "Dijkstra number"2 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepage:

On csauthors.net:

Bibliography

2017
Estimating and understanding architectural risk.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Thermal-aware, heterogeneous materials for improved energy and reliability in 3D PCM architectures.
Proceedings of the International Symposium on Memory Systems, 2017

Challenging on-chip SRAM security with boot-state statistics.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

A pythonic approach for rapid hardware prototyping and instrumentation.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

A 4-mm2 180-nm-CMOS 15-Giga-cell-updates-per-second DNA sequence alignment engine based on asynchronous race conditions.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

An Architecture Supporting Formal and Compositional Binary Analysis.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
Report on the NSF Workshop on Formal Methods for Security.
CoRR, 2016

Energy efficient computation with asynchronous races.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Hardware-Assisted Context Management for Accelerator Virtualization: A Case Study with RSA.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015
Race Logic: Abusing Hardware Race Conditions to Perform Useful Computation.
IEEE Micro, 2015

Quantifying Timing-Based Information Flow in Cryptographic Hardware.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
Gate-Level Information Flow Tracking for Security Lattices.
ACM Trans. Design Autom. Electr. Syst., 2014

Leveraging Gate-Level Properties to Identify Hardware Timing Channels.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Networks on Chip with Provable Security Properties.
IEEE Micro, 2014

Race Logic: A hardware acceleration for dynamic programming algorithms.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Sapper: a language for hardware-level security policy enforcement.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

2013
A 3-D Split Manufacturing Approach to Trustworthy System Development.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Inspection-Resistant Memory Architectures.
IEEE Micro, 2013

Eliminating Timing Information Flows in a Mix-Trusted System-on-Chip.
IEEE Design & Test, 2013

Position paper: Sapper - a language for provable hardware policy enforcement.
Proceedings of the 2013 ACM SIGPLAN Workshop on Programming Languages and Analysis for Security, 2013

SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

A practical testing framework for isolating hardware timing channels.
Proceedings of the Design, Automation and Test in Europe, 2013

Memristors for neural branch prediction: a case study in strict latency and write endurance challenges.
Proceedings of the Computing Frontiers Conference, 2013

2012
On the Complexity of Generating Gate Level Information Flow Tracking Logic.
IEEE Trans. Information Forensics and Security, 2012

Dataflow Tomography: Information Flow Tracking For Understanding and Visualizing Full Systems.
TACO, 2012

Analysis of performance versus security in hardware realizations of small elliptic curves for lightweight applications.
J. Cryptographic Engineering, 2012

Opportunities and Challenges of Using Plasmonic Components in Nanophotonic Architectures.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Mobile Vision-Based Sketch Recognition with SPARK.
Proceedings of the Sketch Based Interfaces and Modeling, 2012

Inspection resistant memory: Architectural support for security from physical examination.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

A Qualitative Security Analysis of a New Class of 3-D Integrated Crypto Co-processors.
Proceedings of the Cryptography and Security: From Theory to Applications, 2012

2011
Theoretical Fundamentals of Gate Level Information Flow Tracking.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Data analysis on interactive whiteboards through sketch-based interaction.
Proceedings of the ACM International Conference on Interactive Tabletops and Surfaces, 2011

Caisson: a hardware description language for secure information flow.
Proceedings of the 32nd ACM SIGPLAN Conference on Programming Language Design and Implementation, 2011

Preventing PCM banks from seizing too much power.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Fighting fire with fire: modeling the datacenter-scale effects of targeted superlattice thermal management.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Exploiting Data Similarity to Reduce Memory Footprints.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Information flow isolation in I2C and USB.
Proceedings of the 48th Design Automation Conference, 2011

Hybrid CMOS/nanodevice circuits for high throughput pattern matching applications.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010
Security Primitives for Reconfigurable Hardware-Based Systems.
TRETS, 2010

Gate-Level Information-Flow Tracking for Secure Architectures.
IEEE Micro, 2010

Sketch-Based Recognition System for General Articulated Skeletal Figures.
Proceedings of the Sketch Based Interfaces and Modeling, Annecy, France, 2010. Proceedings, 2010

Secure information flow analysis for hardware design: using the right abstraction for the job.
Proceedings of the 2010 Workshop on Programming Languages and Analysis for Security, 2010

VrtProf: Vertical Profiling for System Virtualization.
Proceedings of the 43rd Hawaii International International Conference on Systems Science (HICSS-43 2010), 2010

Theoretical analysis of gate level information flow tracking.
Proceedings of the 47th Design Automation Conference, 2010

Hardware trust implications of 3-D integration.
Proceedings of the 5th Workshop on Embedded Systems Security, 2010

Function flattening for lease-based, information-leak-free systems.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

Hardware assistance for trustworthy systems through 3-D integration.
Proceedings of the Twenty-Sixth Annual Computer Security Applications Conference, 2010

2009
High-bandwidth network memory system through virtual pipelines.
IEEE/ACM Trans. Netw., 2009

Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems.
J. Low Power Electronics, 2009

Analysis of Bit-Split Languages for Packet Scanning and Experiments with Wildcard Matching.
Int. J. Found. Comput. Sci., 2009

Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Execution leases: a hardware-supported mechanism for enforcing strong non-interference.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Conflict-Avoidance in Multicore Caching for Data-Similar Executions.
Proceedings of the 10th International Symposium on Pervasive Systems, 2009

Multi-execution: multicore caching for data-similar executions.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Complete information flow tracking from the gates up.
Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, 2009

Quantifying the Potential of Program Analysis Peripherals.
Proceedings of the PACT 2009, 2009

2008
Ternary CAM Power and Delay Model: Extensions and Uses.
IEEE Trans. VLSI Syst., 2008

Designing secure systems on reconfigurable hardware.
ACM Trans. Design Autom. Electr. Syst., 2008

Formulating and implementing profiling over adaptive ranges.
TACO, 2008

Structural integrity: safety in miniature technology.
SIGBED Review, 2008

Managing Security in FPGA-Based Embedded Systems.
IEEE Design & Test of Computers, 2008

Enforcing memory policy specifications in reconfigurable hardware.
Computers & Security, 2008

Automata-Theoretic Analysis of Bit-Split Languages for Packet Scanning.
Proceedings of the Implementation and Applications of Automata, 2008

Exploring the Processor and ISA Design for Wireless Sensor Network Applications.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Whiteboards that compute: A workload analysis.
Proceedings of the 4th International Symposium on Workload Characterization (IISWC 2008), 2008

Trustworthy System Security through 3-D Integrated Hardware.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

Understanding and visualizing full systems with data flow tomography.
Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008

2007
3D Integration for Introspection.
IEEE Micro, 2007

Moats and Drawbridges: An Isolation Primitive for Reconfigurable Hardware Based Systems.
Proceedings of the 2007 IEEE Symposium on Security and Privacy (S&P 2007), 2007

Towards understanding architectural tradeoffs in MEMS closed-loop feedback control.
Proceedings of the 2007 International Conference on Compilers, 2007

2006
Bit-split string-matching engines for intrusion detection and prevention.
TACO, 2006

Efficient remote profiling for resource-constrained devices.
TACO, 2006

Architectures for Bit-Split String Scanning in Intrusion Detection.
IEEE Micro, 2006

Guest Editors' Introduction: Computer Architecture Simulation and Modeling.
IEEE Micro, 2006

Using Machine Learning to Guide Architecture Simulation.
Journal of Machine Learning Research, 2006

An Evaluation of Deeply Decoupled Cores.
J. Instruction-Level Parallelism, 2006

Virtually Pipelined Network Memory.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Modeling TCAM power for next generation network devices.
Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006

Guiding Architectural SRAM Models.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Policy-Driven Memory Protection for Reconfigurable Hardware.
Proceedings of the Computer Security, 2006

Leakage power reduction of embedded memories on FPGAs through location assignment.
Proceedings of the 43rd Design Automation Conference, 2006

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy.
Proceedings of the 43rd Design Automation Conference, 2006

Profiling over Adaptive Ranges.
Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006

Improving the performance and power efficiency of shared helpers in CMPs.
Proceedings of the 2006 International Conference on Compilers, 2006

A case study of multi-threading in the embedded space.
Proceedings of the 2006 International Conference on Compilers, 2006

Extensible control architectures.
Proceedings of the 2006 International Conference on Compilers, 2006

Introspective 3D chips.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

Wavelet-based phase classification.
Proceedings of the 15th International Conference on Parallel Architecture and Compilation Techniques (PACT 2006), 2006

2005
Exploring the limits of leakage power reduction in caches.
TACO, 2005

Dynamically configurable shared CMP helper engines for improved performance.
SIGARCH Computer Architecture News, 2005

Algorithm/Architecture Co-exploration for Designing Energy Efficient Wireless Channel Estimator.
J. Low Power Electronics, 2005

Motivation for Variable Length Intervals and Hierarchical Phase Behavior.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

A High Throughput String Matching Architecture for Intrusion Detection and Prevention.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

On the Limits of Leakage Power Reduction in Caches.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

Data Partitioning and Optimizations for Reconfigurable Architectures.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

MP core: algorithm and design techniques for efficient channel estimation in wireless applications.
Proceedings of the 42nd Design Automation Conference, 2005

Project VIRGO: creation of a surrogate companion for the elderly.
Proceedings of the Extended Abstracts Proceedings of the 2005 Conference on Human Factors in Computing Systems, 2005

Phase-Aware Remote Profiling.
Proceedings of the 3nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2005), 2005

2004
Low-Overhead Core Swapping for Thermal Management.
Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004

A co-phase matrix to guide simultaneous multithreading simulation.
Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software, 2004

Deterministic Memory-Efficient String Matching Algorithms for Intrusion Detection.
Proceedings of the Proceedings IEEE INFOCOM 2004, 2004

Development of an Olympic audience judging system.
Proceedings of the Extended abstracts of the 2004 Conference on Human Factors in Computing Systems, 2004

Balancing design options with Sherpa.
Proceedings of the 2004 International Conference on Compilers, 2004

2003
A Decoupled Predictor-Directed Stream Prefetching Architecture.
IEEE Trans. Computers, 2003

Discovering and Exploiting Program Phases.
IEEE Micro, 2003

Using SimPoint for accurate and efficient simulation.
Proceedings of the International Conference on Measurements and Modeling of Computer Systems, 2003

A Pipelined Memory Architecture for High Throughput Network Processors.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

Phase Tracking and Prediction.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

Catching Accurate Profiles in Hardwar.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

Reducing code size with echo instructions.
Proceedings of the International Conference on Compilers, 2003

2002
Quantifying Load Stream Behavior.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

Automatically characterizing large scale program behavior.
Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), 2002

2001
Bitwidth cognizant architecture synthesis of custom hardwareaccelerators.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Automated design of finite state machine predictors for customized processors.
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

Patchable instruction ROM architecture.
Proceedings of the 2001 International Conference on Compilers, 2001

Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications.
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 2001

2000
Predictor-directed stream buffers.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

Loop Termination Prediction.
Proceedings of the High Performance Computing, Third International Symposium, 2000

ToolBlocks: An Infrastructure for the Construction of Memory Hierarchy Analysis Tools (Research Note).
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

1999
Reducing cache misses using hardware and software page placement.
Proceedings of the 13th international conference on Supercomputing, 1999

ActiveOS: Virtualizing Intelligent Memory.
Proceedings of the IEEE International Conference On Computer Design, 1999

1998
Active Pages: A Computation Model for Intelligent Memory.
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998


  Loading...