Behnam Farnaghinejad

According to our database, Behnam Farnaghinejad authored at least 5 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Case Study: Integrating RISC-V Zicfiss Shadow Stack Support for Control-Flow Integrity on the CVA6 Processor.

Behnam Farnaghinejad, Ernesto Sanchez

Proceedings of the 27th IEEE Latin American Test Symposium, 2026

Deep Learning-Based Power Side-Channel Evaluation from RTL Switching-Activity Proxies.

Behnam Farnaghinejad, Annachiara Ruospo, Alessandro Savino, Stefano Di Carlo, Ernesto Sánchez

Proceedings of the 27th IEEE Latin American Test Symposium, 2026

2025

Power Side-Channel Analysis of the CVA6 RISC-V Core at the RTL Level Using VeriSide.

Behnam Farnaghinejad, Antonio Porsia, Annachiara Ruospo, Alessandro Savino, Stefano Di Carlo, Ernesto Sánchez

CoRR, December, 2025

Late Contribution: VeriSide: A Modified Verilator for Leakage Assessment at the RTL Level.

Behnam Farnaghinejad, Antonio Porsia, Annachiara Ruospo, Alessandro Savino, Stefano Di Carlo, Ernesto Sánchez

Proceedings of the 26th IEEE Latin American Test Symposium, 2025

Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF).

Behnam Farnaghinejad, Davide Bellizia, Alessandra Dolmeta, Guido Masera, Antonio Porsia, Annachiara Ruospo, Stefano Di Carlo, Alessandro Savino, Ernesto Sánchez

Proceedings of the IEEE International Test Conference, 2025