Stefano Di Carlo
Orcid: 0000-0002-7512-5356Affiliations:
- Politecnico di Torino, Italy
According to our database1,
Stefano Di Carlo
authored at least 193 papers
between 2000 and 2024.
Collaborative distances:
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Bibliography
2024
Neuronal Spike Shapes (NSS): A straightforward approach to investigate heterogeneity in neuronal excitability states.
Comput. Biol. Medicine, January, 2024
CoRR, 2024
Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge.
CoRR, 2024
2023
CoRR, 2023
Vitamin-V: Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Services.
CoRR, 2023
NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.
CoRR, 2023
Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Meta-analysis of Gene Activity (MAGA) Contributions and Correlation with Gene Expression, Through GAGAM.
Proceedings of the Bioinformatics and Biomedical Engineering, 2023
EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.
Proceedings of the IEEE European Test Symposium, 2023
Micro-Architectural features as soft-error markers in embedded safety-critical systems: preliminary study.
Proceedings of the IEEE European Test Symposium, 2023
Validation, Verification, and Testing (VVT) of future RISC-V powered cloud infrastructures: the Vitamin-V Horizon Europe Project perspective.
Proceedings of the IEEE European Test Symposium, 2023
Design Space Exploration of Approximate Computing Techniques with a Reinforcement Learning Approach.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023
VITAMIN-V: Virtual Environment and Tool-Boxing for Trustworthy Development of RISC-V Based Cloud Services.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2023
Optimization of synthetic oscillatory biological networks through Reinforcement Learning.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2023
2022
CoRR, 2022
Are micro-architectural features able to explain faulty executions in the presence of soft errors? A preliminary study.
CoRR, 2022
CAN-MM: Multiplexed Message Authentication Code for Controller Area Network message authentication in road vehicles.
CoRR, 2022
Prediction of the Impact of Approximate Computing on Spiking Neural Networks via Interval Arithmetic.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
GAGAM: A Genomic Annotation-Based Enrichment of scATAC-seq Data for Gene Activity Matrix.
Proceedings of the Bioinformatics and Biomedical Engineering, 2022
Proceedings of the Bioinformatics and Biomedical Engineering, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
LIN-MM: Multiplexed Message Authentication Code for Local Interconnect Network message authentication in road vehicles.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
High-resolution sample size enrichment of single-cell multi-modal low-throughput Patch-seq datasets.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2022
Proceedings of the IEEE International Conference on Automation, 2022
Proceedings of the IEEE International Conference on Automation, 2022
2021
Guest Editorial: Special Section on Emerging Trends and Computing Paradigms for Testing, Reliability and Security in Future VLSI Systems.
IEEE Trans. Emerg. Top. Comput., 2021
Special Session: Operating Systems under test: an overview of the significance of the operating system in the resiliency of the computing continuum.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Mitigation of Automotive Control Modules Hardware Replacement-based Attacks Through Hardware Signature.
Proceedings of the 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2021
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Meta-Analysis of cortical inhibitory interneurons markers landscape and their performances in scRNA-seq studies.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2021
2020
IEEE Des. Test, 2020
Proceedings of the 41st IEEE Real-Time Systems Symposium, 2020
Technology-Enhanced Learning (TEL) in Anaesthesia: Ultrasound Simulation Training for Innovative Locoregional Anaesthesia.
Proceedings of the Methodologies and Intelligent Systems for Technology Enhanced Learning, 2020
Design, Verification, Test and In-Field Implications of Approximate Computing Systems.
Proceedings of the IEEE European Test Symposium, 2020
Proceedings of the 50th Annual IEEE-IFIP International Conference on Dependable Systems and Networks, 2020
2019
SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems.
IEEE Trans. Computers, 2019
CoRR, 2019
'One DB to rule them all' - the RING: a Regulatory INteraction Graph combining TFs, genes/proteins, SNPs, diseases and drugs.
Database J. Biol. Databases Curation, 2019
Bayesian models for early cross-layer reliability analysis and design space exploration.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Combining Cluster Sampling and ACE analysis to improve fault-injection based reliability evaluation of GPU-based systems.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019
2018
ReDO: Cross-Layer Multi-Objective Design-Exploration Framework for Efficient Soft Error Resilient Systems.
IEEE Trans. Computers, 2018
Multi-faceted microarchitecture level reliability characterization for NVIDIA and AMD GPUs.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Special session: How approximate computing impacts verification, test and reliability.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Predicting the Impact of Functional Approximation: from Component- to Application-Level.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Shielding Performance Monitor Counters: a double edged weapon for safety and security.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Trading-off reliability and performance in FPGA-based reconfigurable heterogeneous systems.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2018
Securing bitstream integrity, confidentiality and authenticity in reconfigurable mobile heterogeneous systems.
Proceedings of the IEEE International Conference on Automation, 2018
2017
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Microarchitecture level reliability comparison of modern GPU designs: First findings.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017
RT Level vs. Microarchitecture-Level Reliability Assessment: Case Study on ARM(R) Cortex(R)-A9 CPU.
Proceedings of the 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2017
Using multi-level Petri nets models to simulate microbiota resistance to antibiotics.
Proceedings of the 2017 IEEE International Conference on Bioinformatics and Biomedicine, 2017
2016
Simul. Model. Pract. Theory, 2016
CyTRANSFINDER: a Cytoscape 3.3 plugin for three-component (TF, gene, miRNA) signal transduction pathway construction.
BMC Bioinform., 2016
Using Nets-Within-Nets for Modeling Differentiating Cells in the Epigenetic Landscape.
Proceedings of the Bioinformatics and Biomedical Engineering, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
A computationally inferred regulatory heart aging model including post-transcriptional regulations.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2016
FishAPP: A mobile App to detect fish falsification through image processing and machine learning techniques.
Proceedings of the IEEE International Conference on Automation, 2016
2015
SA-FEMIP: A Self-Adaptive Features Extractor and Matcher IP-Core Based on Partially Reconfigurable FPGAs for Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2015
SATTA: A Self-Adaptive Temperature-Based TDF Awareness Methodology for Dynamically Reconfigurable FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2015
Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers.
ACM Trans. Embed. Comput. Syst., 2015
SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview.
Microprocess. Microsystems, 2015
Proceedings of the 4th Mediterranean Conference on Embedded Computing, 2015
A 3D Voxel Neighborhood Classification Approach within a Multiparametric MRI Classifier for Prostate Cancer Detection.
Proceedings of the Bioinformatics and Biomedical Engineering, 2015
Bayesian network early reliability evaluation analysis for both permanent and transient faults.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
2014
FLARES: An Aging Aware Algorithm to Autonomously Adapt the Error Correction Capability in NAND Flash Memories.
ACM Trans. Archit. Code Optim., 2014
Using Boolean networks to model post-transcriptional regulation in gene regulatory networks.
J. Comput. Sci., 2014
IT Prof., 2014
FunMod: A Cytoscape Plugin for Identifying Functional Modules in Undirected Protein-Protein Networks.
Genom. Proteom. Bioinform., 2014
J. Electron. Test., 2014
A novel algorithm and hardware architecture for fast video-based shape reconstruction of space debris.
EURASIP J. Adv. Signal Process., 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 9th International Design and Test Symposium, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
On Enhancing Fault Injection's Capabilities and Performances for Safety Critical Systems.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
A fault injection methodology and infrastructure for fast single event upsets emulation on Xilinx SRAM-based FPGAs.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
A Prostate Cancer Computer Aided Diagnosis Software including Malignancy Tumor Probabilistic Classification.
Proceedings of the BIOIMAGING 2014, 2014
A Computational Pipeline to Identify New Potential Regulatory Motifs in Melanoma Progression.
Proceedings of the Biomedical Engineering Systems and Technologies, 2014
A Computational Study to Identify TP53 and SREBF2 as Regulation Mediators of miR-214 in Melanoma Progression.
Proceedings of the BIOINFORMATICS 2014, 2014
Identifying Sub-Network Functional Modules in Protein Undirected Networks.
Proceedings of the BIOINFORMATICS 2014, 2014
2013
Microprocess. Microsystems, 2013
J. Clin. Bioinform., 2013
Accounting for Post-Transcriptional Regulation in Boolean Networks Based Regulatory Models.
Proceedings of the International Work-Conference on Bioinformatics and Biomedical Engineering, 2013
Proceedings of the International Work-Conference on Bioinformatics and Biomedical Engineering, 2013
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
SAFE: A self adaptive frame enhancer FPGA-based IP-core for real-time space applications.
Proceedings of the 8th International Design and Test Symposium, 2013
Proceedings of the 8th International Design and Test Symposium, 2013
FEMIP: A high performance FPGA-based features extractor & matcher for space applications.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
On the on-line functional test of the Reorder Buffer memory in superscalar processors.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
2012
FPGA-Based Remote-Code Integrity Verification of Programs in Distributed Embedded Systems.
IEEE Trans. Syst. Man Cybern. Part C, 2012
IEEE Trans. Computers, 2012
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Combining homolog and motif similarity data with Gene Ontology relationships for protein function prediction.
Proceedings of the 2012 IEEE International Conference on Bioinformatics and Biomedicine, 2012
2011
A cDNA Microarray Gene Expression Data Classifier for Clinical Diagnostics Based on Graph Theory.
IEEE ACM Trans. Comput. Biol. Bioinform., 2011
IEEE Trans. Computers, 2011
Increasing pattern recognition accuracy for chemical sensing by evolutionary based drift compensation.
Pattern Recognit. Lett., 2011
Sci. China Inf. Sci., 2011
Building gene expression profile classifiers with a simple and efficient rejection option in R.
BMC Bioinform., 2011
Proceedings of the 2011 World Congress on Internet Security, 2011
Proceedings of the 6th IEEE International Design and Test Workshop, 2011
Proceedings of the 6th IEEE International Design and Test Workshop, 2011
Proceedings of the 9th East-West Design & Test Symposium, 2011
Proceedings of the Applications of Evolutionary Computation, 2011
MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
System reliability evaluation using concurrent multi-level simulation of structural faults.
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the Genetic and Evolutionary Computation Conference, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Proceedings of the Applications of Evolutionary Computation, 2010
Proceedings of the 15th European Test Symposium, 2010
Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level.
Proceedings of the 19th IEEE Asian Test Symposium, 2010
2009
IEEE Des. Test Comput., 2009
Proceedings of the 2009 IEEE International Test Conference, 2009
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008
Proceedings of the 13th European Test Symposium, 2008
Proceedings of the 2008 IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology, 2008
Differential gene expression graphs: A data structure for classification in DNA microarrays.
Proceedings of the 8th IEEE International Conference on Bioinformatics and Bioengineering, 2008
Influence of Parasitic Capacitance Variations on 65 nm and 32 nm Predictive Technology Model SRAM Core-Cells.
Proceedings of the 17th IEEE Asian Test Symposium, 2008
Proceedings of the 17th IEEE Asian Test Symposium, 2008
2007
March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs.
IET Comput. Digit. Tech., 2007
Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
2006
Proceedings of the 11th European Test Symposium, 2006
Proceedings of the 11th European Test Symposium, 2006
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 15th Asian Test Symposium, 2006
Proceedings of the 15th Asian Test Symposium, 2006
2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the 10th European Test Symposium, 2005
2004
Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004
2003
PhD thesis, 2003
Programmable built-in self-testing of embedded RAM clusters in system-on-chip architectures.
IEEE Commun. Mag., 2003
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
SEU effect analysis in an open-source router via a distributed fault injection environment.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
HD<sup>2</sup>BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Proceedings of the 5th European Test Workshop, 2000