Davide Bellizia
Orcid: 0000-0002-6947-4410
According to our database1,
Davide Bellizia
authored at least 32 papers
between 2016 and 2023.
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Bibliography
2023
An In-Depth Evaluation of Externally Amplified Coupling (EAC) Attacks - A Concrete Threat for Masked Cryptographic Implementations.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
2022
When Bad News Become Good News Towards Usable Instances of Learning with Physical Errors.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Novel Ultra-Compact FPGA-Compatible TRNG Architecture Exploiting Latched Ring Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
High-Throughput FPGA-Compatible TRNG Architecture Exploiting Multistimuli Metastable Cells.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
2021
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021
J. Cryptogr. Eng., 2021
Cryptogr., 2021
Post-Quantum Cryptography: Challenges and Opportunities for Robust and Secure HW Design.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
Proceedings of the Smart Card Research and Advanced Applications, 2021
2020
Spook: Sponge-Based Leakage-Resistant Authenticated Encryption with a Masked Tweakable Block Cipher.
IACR Trans. Symmetric Cryptol., 2020
IEEE Trans. Circuits Syst., 2020
SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
Int. J. Circuit Theory Appl., 2020
Mode-Level vs. Implementation-Level Physical Security in Symmetric Cryptography: A Practical Guide Through the Leakage-Resistance Jungle.
IACR Cryptol. ePrint Arch., 2020
IACR Cryptol. ePrint Arch., 2020
2019
Reducing a Masked Implementation's Effective Security Order with Setup Manipulations And an Explanation Based on Externally-Amplified Couplings.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019
2018
Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks.
IEEE Trans. Very Large Scale Integr. Syst., 2018
TEL Logic Style as a Countermeasure Against Side-Channel Attacks: Secure Cells Library in 65nm CMOS and Experimental Results.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Univariate Power Analysis Attacks Exploiting Static Dissipation of Nanometer CMOS VLSI Circuits for Cryptographic Applications.
IEEE Trans. Emerg. Top. Comput., 2017
Template attacks exploiting static power and application to CMOS lightweight crypto-hardware.
Int. J. Circuit Theory Appl., 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
Multivariate Analysis Exploiting Static Power on Nanoscale CMOS Circuits for Cryptographic Applications.
Proceedings of the Progress in Cryptology - AFRICACRYPT 2017, 2017
2016
On-chip analog current equalizer as a countermeasure against side-channel attacks in CMOS nanometer technology.
Proceedings of the 2016 MIXDES, 2016
Implementation of the PRESENT-80 block cipher and analysis of its vulnerability to Side Channel Attacks Exploiting Static Power.
Proceedings of the 2016 MIXDES, 2016