Antonio Porsia

Orcid: 0009-0009-4671-5064

According to our database1, Antonio Porsia authored at least 10 papers between 2023 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Emulating SDC-1 Hardware Faults Through Application Level Bit-Flip Injections in QNNs.
Proceedings of the 27th IEEE Latin American Test Symposium, 2026

2025
Power Side-Channel Analysis of the CVA6 RISC-V Core at the RTL Level Using VeriSide.
CoRR, December, 2025

Image Test Libraries for the In-Field Test of Ultra-Low-Power Devices.
Proceedings of the 26th IEEE Latin American Test Symposium, 2025

Late Contribution: VeriSide: A Modified Verilator for Leakage Assessment at the RTL Level.
Proceedings of the 26th IEEE Latin American Test Symposium, 2025

Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF).
Proceedings of the IEEE International Test Conference, 2025

On the Resilience of INT8 Quantized Neural Networks on Low-Power RISC-V Devices.
Proceedings of the 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2025

2024
Resiliency Approaches in Convolutional, Photonic, and Spiking Neural Networks.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024

AI Eye Charts: measuring the visual acuity of Neural Networks with test images.
Proceedings of the IEEE International Conference on Design, 2024

Model theft attack against a tinyML application running on an Ultra-Low-Power Open-Source SoC.
Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024

2023
Image Test Libraries for the on-line self-test of functional units in GPUs running CNNs.
Proceedings of the IEEE European Test Symposium, 2023


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