Behzad Zeinali

According to our database, Behzad Zeinali authored at least 11 papers between 2011 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAMs.

Behzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi

IEEE Trans. Emerg. Top. Comput., 2019

Spin-Orbit-Torque-based Devices, Circuits and Architectures.

Farshad Moradi, Hooman Farkhani, Behzad Zeinali, Hamdam Ghanatian, Johan Michel Alain Pelloux-Prayer, Tim Böhnert, Mohammad Zahedinejad, Hadi Heidari, Vahid Nabaei, Ricardo Ferreira, Johan Åkerman, Jens Kargaard Madsen

CoRR, 2019

2018

Progressive Scaled STT-RAM for Approximate Computing in Multimedia Applications.

Behzad Zeinali, Dimitrios Karsinos, Farshad Moradi

IEEE Trans. Circuits Syst. II Express Briefs, 2018

A Reduced Store/Restore Energy MRAM-Based SRAM Cell for a Non-Volatile Dynamically Reconfigurable FPGA.

Leila Bagheriye, Siroos Toofan, Roghayeh Saeidi, Behzad Zeinali, Farshad Moradi

IEEE Trans. Circuits Syst. II Express Briefs, 2018

2017

Low-leakage sub-threshold 9 T-SRAM cell in 14-nm FinFET technology.

Behzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi

Int. J. Circuit Theory Appl., 2017

Ultra-Fast SOT-MRAM Cell with STT Current for Deterministic Switching.

Behzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Multilevel SOT-MRAM cell with a novel sensing scheme for high-density memory applications.

Behzad Zeinali, Mahsa Esmaeili, Jens Kargaard Madsen, Farshad Moradi

Proceedings of the 47th European Solid-State Device Research Conference, 2017

2015

Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power.

Behzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014

Equalization-Based Digital Background Calibration Technique for Pipelined ADCs.

Behzad Zeinali, Tohid Moosazadeh, Mohammad Yavari, Ángel Rodríguez-Vázquez

IEEE Trans. Very Large Scale Integr. Syst., 2014

8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology.

Farshad Moradi, Mohammad Tohidi, Behzad Zeinali, Jens Kargaard Madsen

Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014

2011

A new digital background correction algorithm with non-precision calibration signals for pipelined ADCs.

Behzad Zeinali, Mohammad Yavari

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011