Besar Asllani

According to our database, Besar Asllani authored at least 3 papers between 2018 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

VTH-Hysteresis and Interface States Characterisation in SiC Power MOSFETs with Planar and Trench Gate.

Besar Asllani, Alberto Castellazzi, Oriol Avino-Salvado, Asad Fayyaz, Hervé Morel, Dominique Planson

Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018

Avalanche ruggedness of parallel SiC power MOSFETs.

Asad Fayyaz, Besar Asllani, Alberto Castellazzi, Michele Riccio, Andrea Irace

Microelectron. Reliab., 2018

<i>V</i>_<i>TH</i> subthreshold hysteresis technology and temperature dependence in commercial 4H-SiC MOSFETs.

Besar Asllani, Asad Fayyaz, Alberto Castellazzi, Hervé Morel, Dominique Planson

Microelectron. Reliab., 2018