Bhaskar Chatterjee

According to our database1, Bhaskar Chatterjee authored at least 9 papers between 2002 and 2005.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2005
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies.
Microelectron. J., 2005

2004
DFT for Delay Fault Testing of High-Performance Digital Circuits.
IEEE Des. Test Comput., 2004

A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Modeling and designing energy-delay optimized wide domino circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2002
A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002


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