Augusli Kifli

According to our database1, Augusli Kifli authored at least 11 papers between 1992 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2015
SoC test integration platform.
Proceedings of the VLSI Design, Automation and Test, 2015

2010
Test cycle power optimization for scan-based designs.
Proceedings of the 2011 IEEE International Test Conference, 2010

A scalable quantitative measure of IR-drop effects for scan pattern generation.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009
Power scan: DFT for power switches in VLSI designs.
Proceedings of the 2009 IEEE International Test Conference, 2009

A Practical DFT Approach for Complex Low Power Designs.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Fault modeling and testing of retention flip-flops in low power designs.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
High Quality Pattern Generation for Delay Defects with Functional Sensitized Paths.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

1995
Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures.
VLSI Signal Processing, 1995

A unified scheduling model for high-level synthesis and code generation.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Chess: retargetable code generation for embedded DSP processors.
Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

1992
Flag/Condition Handling and Branch Assignment for Large Microcoded Controllers.
Proceedings of the Synthesis for Control Dominated Circuits, 1992


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