Cheong-Fat Chan

According to our database1, Cheong-Fat Chan authored at least 64 papers between 1994 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2009
A Novel Mismatch Cancellation and I/Q Channel Multiplexing Scheme for Quadrature Bandpass DeltaSigma Modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A Fully Differential Band-Selective Low-Noise Amplifier for MB-OFDM UWB Receivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Enhanced channel selection using digital low-IF in Weaver receiver architecture.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A Speech Recognition IC Using Hidden Markov Models with Continuous Observation Densities.
J. VLSI Signal Process., 2007

Power-Efficient VLSI Realization of a Complex FSM for H.264/AVC Bitstream Parsing.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Priority-Based Heading One Detector in H.264/AVC Decoding.
EURASIP J. Embed. Syst., 2007

2006
A 75-dB image rejection IF-input quadrature-sampling SC ΣΔ Modulator.
IEEE J. Solid State Circuits, 2006

Power-efficient VLSI implementation of bitstream parsing in H.264/AVC decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A fully differential low noise amplifier with real-time channel hopping for ultra-wideband wireless applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An optimal normal basis elliptic curve cryptoprocessor for inductive RFID application.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 0.5V fully differential OTA with local common feedback.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An efficient MFCC extraction method in speech recognition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 6-digit CMOS current-mode analog-to-quaternary converter with RSD error correction algorithm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Adiabatic Smart Card.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

0.7 V Monolithic CMOS LNA for 802.11 A/B WLAN Application.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

0.8 V GPS band CMOS VCO with 29% Tuning Range.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Sub-1 V Current Mode CMOS Integrated Receiver Front-end for GPS System.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Active RC filter with reduced capacitance by current division technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Ramp voltage supply using adiabatic charging principle.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Realization of card-centric framework: a card-centric computer [smart cards].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A speech recognizer with selectable model parameters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 75dB image rejection IF-input quadrature sampling SC ΣΔ modulator.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004
High Speed Curve Interpolating D/A Converter.
J. VLSI Signal Process., 2004

Preparing smartcard for the future: from passive to active.
IEEE Trans. Consumer Electron., 2004

An I/Q mismatch-free switched-capacitor complex sigma-delta Modulator.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

A low-latency asynchronous shift register.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

A high-efficiency strongly self-checking asynchronous datapath.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Pipelines in Dynamic Dual-Rail Circuits.
Proceedings of the Integrated Circuit and System Design, 2004

An IF-sampling SC complex lowpass Sigma Delta modulator with high image rejection by capacitor sharing.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An asynchronous SOVA decoder for wireless communication application.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An IF input continuous-time sigma-delta analog-digital converter with high image rejection.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Card-Centric Framework - Providing I/O Resources for Smart Cards.
Proceedings of the Smart Card Research and Advanced Applications VI, 2004

A low power asynchronous Java processor for contactless smart card.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Reversed nested Miller compensation with voltage buffer and nulling resistor.
IEEE J. Solid State Circuits, 2003

Design for Self-Checking and Self-Timed Datapath.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Clock recovery circuit with adiabatic technology (quasi-static CMOS logic).
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A low power asynchronous GF(2<sup>173</sup>) ALU for elliptic curve crypto-processor.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An HMM-based speech recognition IC.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
A 12-bit 80 Ms/s 110 mW floating analog-to-digital converter.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A quadrature IF mixer with high image rejection for continuous-time complex Sigma-Delta modulators.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A CMOS current feedback operational amplifier with active current mode compensation.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A 1.2 V 900 MHz CMOS mixer.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A Totally Self-Checking Dynamic Asynchronous Datapath.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

A 900 MHz 1.2 V CMOS mixer with high linearity.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
A New Control Circuit for Asynchronous Micropipelines.
IEEE Trans. Computers, 2001

A self-timed divider using a new fast and robust pipeline scheme.
IEEE J. Solid State Circuits, 2001

Asynchronous cross-pipelined multiplier.
IEEE J. Solid State Circuits, 2001

A low power asynchronous DES.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A giga-hertz CMOS digital controlled oscillator.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A pipelined dataflow small micro-coded asynchronous processor and its application to DCT.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
High speed CMOS digital-to-analog converter with linear interpolator.
IEEE Trans. Consumer Electron., 2000

CMOS high speed interpolators based on parallel architecture.
IEEE Trans. Consumer Electron., 2000

An ALU design using a novel asynchronous pipeline architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

An 8×8 adiabatic quasi-static CMOS multiplier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Design of self-timed asynchronous Booth's multiplier.
Proceedings of ASP-DAC 2000, 2000

1999
A self-timed ICT chip for image coding.
IEEE Trans. Circuits Syst. Video Technol., 1999

A four-phase handshaking asynchronous static RAM design for self-timed systems.
IEEE J. Solid State Circuits, 1999

Pipelined Dataflow Architecture of a Small Processor.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

1998
Asynchronous logic in bit-serial arithmetic.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

A Useful Micropipeline Architecture to Implement DSP Algorithms.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997
Self-timed 1-D ICT processor.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Test Generation with Dynamic Probe Points in High Observability Testing Environment.
IEEE Trans. Computers, 1996

1995
A Feedback Control Circuit Design Technique to Suppress Power Noise in High Speed Output Driver.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Hardware emulation board based on FPGAs and programmable interconnections.
Proceedings of IEEE 5th International Workshop on Rapid System Prototyping, 1994


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