Oliver Chiu-sing Choy

According to our database1, Oliver Chiu-sing Choy authored at least 103 papers between 1994 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
BOTDA Fiber Sensor System Based on FPGA Accelerated Support Vector Regression.
IEEE Trans. Instrum. Meas., 2020

2019
A 0.4 V 298 nJ/op Neural Signal Spectral Feature Extraction Module With Novel Approximate MACs and Custom Compressors.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Brillouin Optical Time Domain Analyzer Fiber Sensor Based on FPGA Accelerated Support Vector Regression.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

2018
A 0.35 V 376 Mb/s Configurable Long Integer Multiplier for Subthreshold Encryption.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Hardware Design of Real Time Epileptic Seizure Detection Based on STFT and SVM.
IEEE Access, 2018

Spatial temporal GRU convnets for vision-based real time epileptic seizure detection.
Proceedings of the 15th IEEE International Symposium on Biomedical Imaging, 2018

2017
Integrating channel selection and feature selection in a real time epileptic seizure detection system.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

2016
Cascaded Network Body Channel Model for Intrabody Communication.
IEEE J. Biomed. Health Informatics, 2016

A 0.4V 320Mb/s 28.7µW 1024-bit configurable multiplier for subthreshold SOC encryption.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Deep sparse rectifier neural networks for speech denoising.
Proceedings of the IEEE International Workshop on Acoustic Signal Enhancement, 2016

Subthreshold Passive RFID Tag's Baseband Processor Core Design with Custom Modules and Cells.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Automatic seizure detection using correlation integral with nonlinear adaptive denoising and Kalman filter.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

2015
A 5.4-mW 180-cm Transmission Distance 2.5-Mb/s Advanced Techniques-Based Novel Intrabody Communication Receiver Analog Front End.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Subthreshold passive RFID tag's baseband processor core design with custom modules and cells.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014
A novel ratioed logic style for faster subthreshold digital circuits based on 90 nm CMOS and below.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

A 2.5-Mbps, 170-cm transmission distance IntraBody communication receiver front end design and its synchronization technique research.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A novel high speed, low power IntraBody Communication Receiver Front End based on sampling rate boosting switched-capacitor filter.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Subthreshold passive RF tag's PIE decoder design with wide tolerance and custom ratioed logic cells.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Simplifying HOG arithmetic for speedy hardware realization.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Architecture and Design Flow for a Highly Efficient Structured ASIC.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A data compression based power aware BAN system exploration of IEEE 802.15.6.
Proceedings of the IEEE International Symposium on Consumer Electronics, 2013

Key component designs of subthreshold baseband processors in passive RF device.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

The Impact of Nodes Embedded with Data Processing Unit on Energy Consumption in a Wireless BAN.
Proceedings of the 4th International Conference on Ambient Systems, 2013

2012
Design a Low-Power H.264/AVC Baseline Decoder at All Abstraction Levels - A Showcase.
J. Signal Process. Syst., 2012

Robust, Low-Complexity, and Energy Efficient Downlink Baseband Receiver Design for MB-OFDM UWB System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A process-compatible passive RFID tag's digital design for subthreshold operation.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
Robust and efficient baseband receiver design for MB-OFDM UWB system.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding.
J. Signal Process. Syst., 2010

A Low-Power Continuously-Calibrated Clock Recovery Circuit for UHF RFID EPC Class-1 Generation-2 Transponders.
IEEE J. Solid State Circuits, 2010

RF Module Design of Passive UHF RFID Tag Implemented in CMOS 90-nm Technology.
J. Low Power Electron., 2010

A low-latency NoC router with lookahead bypass.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Structured ASIC: Methodology and comparison.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Design of a single layer programmable Structured ASIC library.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Rapid prototyping on a structured ASIC fabric.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Performance evaluation of OFDM de-modulator with various multiplier architectures for UWB system.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Low-Cost Allocator Implementations for Networks-on-Chip Routers.
VLSI Design, 2009

Low-Power Bitstream-Residual Decoder for H.264/AVC Baseline Profile Decoding.
EURASIP J. Embed. Syst., 2009

A Novel Mismatch Cancellation and I/Q Channel Multiplexing Scheme for Quadrature Bandpass DeltaSigma Modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Robust and Low Complexity Packet Detector Design for MB-OFDM UWB.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Low-power Signal Processing Front-end and Decoder for UHF Passive RFID Transponders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A comparison of via-programmable gate array logic cell circuits.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008
A Power-Efficient and Self-Adaptive Prediction Engine for H.264/AVC Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2008

A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC.
IEEE Trans. Circuits Syst. Video Technol., 2008

A Fully Differential Band-Selective Low-Noise Amplifier for MB-OFDM UWB Receivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Low-Cost VC Allocator Design for Virtual Channel Wormhole Routers in Networks-on-Chip.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Design of passive UHF RFID tag in 130nm CMOS technology.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Enhanced channel selection using digital low-IF in Weaver receiver architecture.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A Speech Recognition IC Using Hidden Markov Models with Continuous Observation Densities.
J. VLSI Signal Process., 2007

Power-Efficient VLSI Realization of a Complex FSM for H.264/AVC Bitstream Parsing.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Priority-Based Heading One Detector in H.264/AVC Decoding.
EURASIP J. Embed. Syst., 2007

Low-power H.264/AVC baseline decoder for portable applications.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

2006
Power-efficient VLSI implementation of bitstream parsing in H.264/AVC decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An ECG measurement IC using driven-right-leg circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A fully differential low noise amplifier with real-time channel hopping for ultra-wideband wireless applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An optimal normal basis elliptic curve cryptoprocessor for inductive RFID application.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 0.5V fully differential OTA with local common feedback.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An efficient MFCC extraction method in speech recognition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 6-digit CMOS current-mode analog-to-quaternary converter with RSD error correction algorithm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Adiabatic Smart Card.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

0.8 V GPS band CMOS VCO with 29% Tuning Range.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Sub-1 V Current Mode CMOS Integrated Receiver Front-end for GPS System.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Active RC filter with reduced capacitance by current division technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Ramp voltage supply using adiabatic charging principle.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Realization of card-centric framework: a card-centric computer [smart cards].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A speech recognizer with selectable model parameters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
High Speed Curve Interpolating D/A Converter.
J. VLSI Signal Process., 2004

Preparing smartcard for the future: from passive to active.
IEEE Trans. Consumer Electron., 2004

An I/Q mismatch-free switched-capacitor complex sigma-delta Modulator.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

A low-latency asynchronous shift register.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

A high-efficiency strongly self-checking asynchronous datapath.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Pipelines in Dynamic Dual-Rail Circuits.
Proceedings of the Integrated Circuit and System Design, 2004

An IF-sampling SC complex lowpass Sigma Delta modulator with high image rejection by capacitor sharing.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An asynchronous SOVA decoder for wireless communication application.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An IF input continuous-time sigma-delta analog-digital converter with high image rejection.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Card-Centric Framework - Providing I/O Resources for Smart Cards.
Proceedings of the Smart Card Research and Advanced Applications VI, 2004

A low power asynchronous Java processor for contactless smart card.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Design for Self-Checking and Self-Timed Datapath.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Clock recovery circuit with adiabatic technology (quasi-static CMOS logic).
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A low power asynchronous GF(2/sup 173/) ALU for elliptic curve crypto-processor.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An HMM-based speech recognition IC.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
A 12-bit 80 Ms/s 110 mW floating analog-to-digital converter.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A quadrature IF mixer with high image rejection for continuous-time complex Sigma-Delta modulators.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A CMOS current feedback operational amplifier with active current mode compensation.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A 1.2 V 900 MHz CMOS mixer.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A Totally Self-Checking Dynamic Asynchronous Datapath.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

A 900 MHz 1.2 V CMOS mixer with high linearity.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
A New Control Circuit for Asynchronous Micropipelines.
IEEE Trans. Computers, 2001

A low power asynchronous DES.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A giga-hertz CMOS digital controlled oscillator.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A pipelined dataflow small micro-coded asynchronous processor and its application to DCT.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
High speed CMOS digital-to-analog converter with linear interpolator.
IEEE Trans. Consumer Electron., 2000

CMOS high speed interpolators based on parallel architecture.
IEEE Trans. Consumer Electron., 2000

An ALU design using a novel asynchronous pipeline architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Design of self-timed asynchronous Booth's multiplier.
Proceedings of ASP-DAC 2000, 2000

1999
A self-timed ICT chip for image coding.
IEEE Trans. Circuits Syst. Video Technol., 1999

Pipelined Dataflow Architecture of a Small Processor.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

1998
A Useful Micropipeline Architecture to Implement DSP Algorithms.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997
Self-timed 1-D ICT processor.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Incremental layout placement modification algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Test Generation with Dynamic Probe Points in High Observability Testing Environment.
IEEE Trans. Computers, 1996

1995
A Feedback Control Circuit Design Technique to Suppress Power Noise in High Speed Output Driver.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Hardware emulation board based on FPGAs and programmable interconnections.
Proceedings of IEEE 5th International Workshop on Rapid System Prototyping, 1994


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