Bing-Yang Lin

According to our database1, Bing-Yang Lin authored at least 19 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
TangleSim: An Agent-based, Modular Simulator for DAG-based Distributed Ledger Technologies.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2023

2022
Robustness of the Tangle 2.0 Consensus.
Proceedings of the Performance Evaluation Methodologies and Tools, 2022

2017
A Built-Off Self-Repair Scheme for Channel-Based 3D Memories.
IEEE Trans. Computers, 2017

Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package.
IEEE Des. Test, 2017

Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache.
IEEE Des. Test, 2017

Highly reliable and low-cost symbiotic IOT devices and systems.
Proceedings of the IEEE International Test Conference, 2017

Symbiotic system models for efficient IGT system design and test.
Proceedings of the International Test Conference in Asia, 2017

2016
A Local Parallel Search Approach for Memory Failure Pattern Identification.
IEEE Trans. Computers, 2016

Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement.
IEEE Des. Test, 2016

A fast sweep-line-based failure pattern extractor for memory diagnosis.
Proceedings of the 21th IEEE European Test Symposium, 2016

Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
System-level test coverage prediction by structural stress test data mining.
Proceedings of the VLSI Design, Automation and Test, 2015

2014
On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs.
IEEE Des. Test, 2014

Location service and session mobility for streaming media applications in home networks.
Comput. Stand. Interfaces, 2014

Redundancy architectures for channel-based 3D DRAM yield improvement.
Proceedings of the 2014 International Test Conference, 2014

2013
Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
A Memory Failure Pattern Analyzer for memory diagnosis and repair.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

2010
Supporting Multimedia Applications in Home Networks using SIP and SLP.
Proceedings of the DCNET 2010 & OPTICS 2010 - Proceedings of the International Conference on Data Communication Networking and International Conference on Optical Communication Systems, Athens, Greece, July 26, 2010


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