Chun-Chuan Chi

According to our database1, Chun-Chuan Chi authored at least 12 papers between 2009 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2014
Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base.
IEEE Trans. Very Large Scale Integr. Syst., 2014

On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs.
IEEE Des. Test, 2014

2013
3D-IC interconnect test, diagnosis, and repair.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2012
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper.
J. Electron. Test., 2012

3D-IC BISR for stacked memories using cross-die spares.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2011
Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base.
Proceedings of the 2011 IEEE International Test Conference, 2011

DfT Architecture for 3D-SICs with Multiple Towers.
Proceedings of the 16th European Test Symposium, 2011

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing.
Proceedings of the 48th Design Automation Conference, 2011

Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
A low-cost and scalable test architecture for multi-core chips.
Proceedings of the 15th European Test Symposium, 2010

3D DfT architecture for pre-bond and post-bond testing.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
Test Integration for SOC Supporting Very Low-Cost Testers.
Proceedings of the Eighteentgh Asian Test Symposium, 2009


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