Mincent Lee

According to our database1, Mincent Lee authored at least 16 papers between 2011 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2022
A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

2020
A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices.
Proceedings of the IEEE International Test Conference, 2020

Site-aware Anomaly Detection with Machine Learning for Circuit Probing to Prevent Overkill.
Proceedings of the IEEE International Test Conference in Asia, 2020

2019
High Quality Test Methodology for Highly Reliable Devices.
Proceedings of the IEEE International Test Conference, 2019

2017
A Built-Off Self-Repair Scheme for Channel-Based 3D Memories.
IEEE Trans. Computers, 2017

Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package.
IEEE Des. Test, 2017

2016
A Local Parallel Search Approach for Memory Failure Pattern Identification.
IEEE Trans. Computers, 2016

Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement.
IEEE Des. Test, 2016

Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2014
A novel DFT architecture for 3DIC test, diagnosis and repair.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Redundancy architectures for channel-based 3D DRAM yield improvement.
Proceedings of the 2014 International Test Conference, 2014

2013
Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
A Memory Failure Pattern Analyzer for memory diagnosis and repair.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Cost modeling and analysis for interposer-based three-dimensional IC.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

A memory yield improvement scheme combining built-in self-repair and error correction codes.
Proceedings of the 2012 IEEE International Test Conference, 2012

2011
A Memory Built-In Self-Repair Scheme Based on Configurable Spares.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011


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