Bo Marr

According to our database1, Bo Marr authored at least 9 papers between 2006 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
Assessing Trends in Performance per Watt for Signal Processing Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Optimizing simulation speed of FPGA model-based synthesis.
Proceedings of the 2016 IEEE High Performance Extreme Computing Conference, 2016

2013
Scaling Energy Per Operation via an Asynchronous Pipeline.
IEEE Trans. Very Large Scale Integr. Syst., 2013

An Asynchronous Dataflow Signal Processing Architecture to Minimize Energy per Op.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

2010
Error Immune Logic for Low-Power Probabilistic Computing.
VLSI Design, 2010

2009
An Asynchronously Embedded Datapath for Performance Acceleration and Energy Efficiency.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A learning digital computer.
Proceedings of the 46th Design Automation Conference, 2009

2006
Probabilistic Design: A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Probabilistic arithmetic and energy efficient embedded signal processing.
Proceedings of the 2006 International Conference on Compilers, 2006


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