Brian P. Degnan

Orcid: 0000-0002-6567-6998

According to our database1, Brian P. Degnan authored at least 20 papers between 2005 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
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PhD thesis 
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Links

Online presence:

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Bibliography

2020
Backscatter Ex-Nihilo: Single-component, Fully-passive Backscattering for Microcontrollers.
Proceedings of the IEEE International Conference on RFID, 2020

2017
A better channel code than FM0 for next-generation RFID.
Proceedings of the 2017 IEEE International Conference on RFID, 2017

On the Simon Cipher 4-block key schedule as a hash.
Proceedings of the 2017 IEEE International Conference on RFID, 2017

2016
Assessing Trends in Performance per Watt for Signal Processing Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2016

On the temperature dependence of subthreshold currents in MOS electron inversion layers, revisited.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Asynchronous trigger modulation for RFID systems.
Proceedings of the IEEE International Conference on RFID Technology and Applications, 2015

A 45 μW bias power, 34 dB gain reflection amplifier exploiting the tunneling effect for RFID applications.
Proceedings of the 2015 IEEE International Conference on RFID, 2015

Low-power, serial interface for power-constrained devices.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

2013
Scaling Energy Per Operation via an Asynchronous Pipeline.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A Learning-Enabled Neuron Array IC Based Upon Transistor Channel Models of Biological Phenomena.
IEEE Trans. Biomed. Circuits Syst., 2013

2010
Error Immune Logic for Low-Power Probabilistic Computing.
VLSI Design, 2010

Reducing offset errors in MITE systems by precise floating gate programming.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Hardware and software infrastructure for a family of floating-gate based FPAAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Live demonstration: Hardware and software infrastructure for a family of floating-gate based FPAAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Crossbar switch matrix for floating-gate programming over large current ranges.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
An Asynchronously Embedded Datapath for Performance Acceleration and Energy Efficiency.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Passgate Resistance Estimation based on the Compact EKV Model and Effective Mobility.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2007
Indirect Programming of Floating-Gate Transistors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Capacitively-Biased Floating-Gate CMOS: a New Logic Family.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005
Programmable floating-gate techniques for CMOS inverters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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