Bo Zhang
Orcid: 0000-0003-3215-8745Affiliations:
- University of Southern California, Department of Electrical and Computer Engineering, Los Angeles, CA, USA
According to our database1,
Bo Zhang authored at least 14 papers
between 2018 and 2026.
Collaborative distances:
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Bibliography
2026
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2026
An Efficient and Scalable Hardware Architecture for Number Theoretic Transform on FPGA with Design Automation.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026
2025
ALLMod: Exploring Area-Efficiency of LUT-based Large Number Modular Reduction via Hybrid Workloads.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024
Design of a High-Performance Iterative Barrett Modular Multiplier for Crypto Systems.
IEEE Trans. Very Large Scale Integr. Syst., May, 2024
A High-Performance, Conflict-Free Memory-Access Architecture for Modular Polynomial Multiplication.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024
2023
IEEE Trans. Computers, 2023
IACR Cryptol. ePrint Arch., 2023
2022
IEEE Trans. Computers, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021
2020
A Timing Uncertainty-Aware Clock Tree Topology Generation Algorithm for Single Flux Quantum Circuits.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018