Bob Schell

According to our database, Bob Schell authored at least 7 papers between 2007 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2020

16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter.

Hajime Shibata, Gerry Taylor, Bob Schell, Victor Kozlov, Sharvil Patil, Donald Paterson, Asha Ganesan, Yunzhi Dong, Wenhua Yang, Yue Yin, Zhao Li, Prawal Shrestha, Athreya Gopal, Aathreya Bhat, Shanthi Pavan

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018

A 3-12.5 Gb/s Reference-Less CDR for an Eye-Opening Monitor.

Bob Schell, Robert Bishop, Jack Kenney

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2009

Analysis and simulation of continuous-time digital signal processors.

Bob Schell, Yannis P. Tsividis

Signal Process., 2009

2008

A Continuous-Time ADC/DSP/DAC System With No Clock and With Activity-Dependent Power Dissipation.

Bob Schell, Yannis P. Tsividis

IEEE J. Solid State Circuits, 2008

A Low Power Tunable Delay Element Suitable for Asynchronous Delays of Burst Information.

Bob Schell, Yannis P. Tsividis

IEEE J. Solid State Circuits, 2008

A Clockless ADC/DSP/DAC System with Activity-Dependent Power Dissipation and No Aliasing.

Bob Schell, Yannis P. Tsividis

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

Analysis of Continuous-Time Digital Signal Processors.

Bob Schell, Yannis P. Tsividis

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007