Bonan Zhang
Orcid: 0000-0003-0605-6032
  According to our database1,
  Bonan Zhang
  authored at least 20 papers
  between 2019 and 2025.
  
  
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
  2025
    CoRR, September, 2025
    
  
UAV-VL-R1: Generalizing Vision-Language Models via Supervised Fine-Tuning and Multi-Stage GRPO for UAV Visual Reasoning.
    
  
    CoRR, August, 2025
    
  
A Fully Row/Column-Parallel MRAM in-Memory Computing Macro With Memory-Resistance Boosting and Weighted Multi-Column ADC Readout.
    
  
    IEEE J. Solid State Circuits, May, 2025
    
  
Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation.
    
  
    IEEE J. Solid State Circuits, March, 2025
    
  
A novel dictionary attack on ECG authentication system using adversarial optimization and clustering.
    
  
    Knowl. Based Syst., 2025
    
  
Cue RAG: Dynamic multi-output cue memory under H framework for retrieval-augmented generation.
    
  
    Neurocomputing, 2025
    
  
    Comput. Secur., 2025
    
  
    Comput. Commun., 2025
    
  
  2024
A Fully Row/Column-Parallel In-Memory Computing Macro in Foundry MRAM With Differential Readout for Noise Rejection.
    
  
    IEEE J. Solid State Circuits, July, 2024
    
  
Clustering-based Evaluation Framework of Feature Extraction Approaches for ECG Biometric Authentication.
    
  
    Proceedings of the International Joint Conference on Neural Networks, 2024
    
  
Reshape and Adapt for Output Quantization (RAOQ): Quantization-aware Training for In-memory Computing Systems.
    
  
    Proceedings of the Forty-first International Conference on Machine Learning, 2024
    
  
Exploring the Vulnerability of ECG-Based Authentication Systems Through A Dictionary Attack Approach.
    
  
    Proceedings of the Algorithms and Architectures for Parallel Processing, 2024
    
  
  2023
Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation.
    
  
    Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
    
  
A 256-kb Fully Row/Column-parallel 22nm MRAM In-Memory-Computing Macro with Differential Readout for Robust Parallelization and Scale-up.
    
  
    Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
    
  
  2022
A 22nm 128-kb MRAM Row/Column-Parallel In-Memory Computing Macro with Memory-Resistance Boosting and Multi-Column ADC Readout.
    
  
    Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
    
  
    Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
    
  
  2021
    IEEE Trans. Circuits Syst. I Regul. Pap., 2021
    
  
A Maximally Row-Parallel MRAM In-Memory-Computing Macro Addressing Readout Circuit Sensitivity and Area.
    
  
    Proceedings of the 47th ESSCIRC 2021, 2021
    
  
    Proceedings of the Cyberspace Safety and Security - 13th International Symposium, 2021
    
  
  2019
Stochastic Data-driven Hardware Resilience to Efficiently Train Inference Models for Stochastic Hardware Implementations.
    
  
    Proceedings of the IEEE International Conference on Acoustics, 2019