Peter Deaville

Orcid: 0000-0001-8029-1060

According to our database1, Peter Deaville authored at least 8 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A Fully Row/Column-Parallel In-Memory Computing Macro in Foundry MRAM With Differential Readout for Noise Rejection.
IEEE J. Solid State Circuits, July, 2024

2023
Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

A 256-kb Fully Row/Column-parallel 22nm MRAM In-Memory-Computing Macro with Differential Readout for Robust Parallelization and Scale-up.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022
A 22nm 128-kb MRAM Row/Column-Parallel In-Memory Computing Macro with Memory-Resistance Boosting and Multi-Column ADC Readout.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Statistical computing framework and demonstration for in-memory computing systems.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
A Maximally Row-Parallel MRAM In-Memory-Computing Macro Addressing Readout Circuit Sensitivity and Area.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2019
MADS: A Framework for Design and Implementation of Adaptive Digital Predistortion Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

A Framework for Design and Implementation of Adaptive Digital Predistortion Systems.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019


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